公开(公告)号：US20080088635A1

公开(公告)日：2008-04-17

申请号：US11833533

申请日：2007-08-03

Applicant: Edward Callway ,  David Glen ,  Andrew Gruber ,  Gaurav Arora ,  Philip Swan

Inventor： Edward Callway ,  David Glen ,  Andrew Gruber ,  Gaurav Arora ,  Philip Swan

IPC: G06T1/00

CPC classification number: H04N5/46 ,  H04N5/14 ,  H04N21/42607 ,  H04N21/42653 ,  H04N21/44008

Abstract: A video graphics chip includes a graphics module configured to process incoming video information in accordance with different modes to produce a video output signal and to transmit the video output signal toward a display screen for rendering of video corresponding to the video information, and a display mode module coupled to the graphics module configured to analyze the incoming video information to determine a type of video associated with the incoming video information and to send a video mode indication of a preferred video processing mode for the incoming video information to the graphics module, where the graphics module is configured to process the incoming video information in accordance with a selected mode from the plurality of different modes based on the video mode indication received from the display module.

Abstract translation: 视频图形芯片包括：图形模块，被配置为根据不同的模式处理输入的视频信息以产生视频输出信号，并将视频输出信号发送到用于呈现与视频信息相对应的视频的显示屏幕;以及显示模式 模块，被配置为分析输入视频信息以确定与输入视频信息相关联的视频的类型，并且将用于输入视频信息的优选视频处理模式的视频模式指示发送到图形模块，其中， 图形模块被配置为基于从显示模块接收的视频模式指示，根据来自多个不同模式的选择模式处理输入视频信息。

公开(公告)号：US07281122B2

公开(公告)日：2007-10-09

申请号：US10756853

申请日：2004-01-14

Applicant: Norman Rubin ,  Andrew Gruber

Inventor： Norman Rubin ,  Andrew Gruber

IPC: G06F11/10

CPC classification number: G06F9/325 ,  G06F9/30072 ,  G06F9/3885

Abstract: A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further includes a first memory device storing a plurality of instructions wherein each of the plurality of instructions includes a plurality of extra bits. The processor is operative to execute the instructions based on the extra bits and in conjunction with a context bit. The method and apparatus further includes a second memory device, such as a general purpose register operably coupled to the processor, the second memory device receiving an incrementing counter instruction upon the execution of one of the plurality of instructions. As such, the method and apparatus allows for nested control flow through a single context bit in conjunction with instructions having a plurality of extra bits.

Abstract translation: 用于嵌套控制流的方法和装置包括具有至少一个上下文比特的处理器。 处理器包括用于执行单指令多数据（SIMD）操作的多个算术逻辑单元。 该方法和装置还包括存储多个指令的第一存储器件，其中多个指令中的每一个指令包括多个额外的位。 处理器可操作以基于额外的比特并结合上下文比特来执行指令。 所述方法和装置还包括第二存储器装置，诸如可操作地耦合到处理器的通用寄存器，第二存储器装置在执行多个指令之一时接收递增计数器指令。 因此，该方法和装置允许通过单个上下文比特结合具有多个额外比特的指令来嵌套控制流。

公开(公告)号：US20050210172A1

公开(公告)日：2005-09-22

申请号：US10791519

申请日：2004-03-02

Applicant: Andrew Gruber ,  Stephen Morein

Inventor： Andrew Gruber ,  Stephen Morein

IPC: G06F3/14 ,  G06F11/00 ,  G06F13/00 ,  G09G5/36

CPC classification number: G06F9/544 ,  G06F3/14 ,  G06F9/542 ,  G09G5/363

Abstract: A method and apparatus for processing real time command information includes a real time event engine that monitors event signals. A real time event detector within the real time event engine detects when the real time event occurs. Thereupon, real time event commands within a real time event command buffer are fetched and consumed by the command processor in response to the occurrence of the real time event. The real time event detector contains a plurality of control registers, which contain an event selector register, a real time command buffer point register, and a real time command buffer length register. A driver may program the registers, whereupon a singe real time event detector may be used in conjunction with a plurality of real time event command buffers.

Abstract translation: 用于处理实时命令信息的方法和装置包括监视事件信号的实时事件引擎。 实时事件引擎中的实时事件检测器检测何时发生实时事件。 因此，响应于实时事件的发生，由命令处理器获取并消耗实时事件命令缓冲器内的实时事件命令。 实时事件检测器包含多个控制寄存器，其包含事件选择器寄存器，实时命令缓冲器点寄存器和实时命令缓冲器长度寄存器。 驱动器可以对寄存器进行编程，因此可以结合多个实时事件命令缓冲器使用单个实时事件检测器。

公开(公告)号：US09256429B2

公开(公告)日：2016-02-09

申请号：US13624657

申请日：2012-09-21

Applicant: Lin Chen ,  Yun Du ,  Andrew Gruber

Inventor： Lin Chen ,  Yun Du ,  Andrew Gruber

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887

Abstract: This disclosure describes techniques for selectively activating a resume check operation in a single instruction, multiple data (SIMD) processing system. A processor is described that is configured to selectively enable or disable a resume check operation for a particular instruction based on information included in the instruction that indicates whether a resume check operation is to be performed for the instruction. A compiler is also described that is configured to generate compiled code which, when executed, causes a resume check operation to be selectively enabled or disabled for particular instructions. The compiled code may include one or more instructions that each specify whether a resume check operation is to be performed for the respective instruction. The techniques of this disclosure may be used to reduce the power consumption of and/or improve the performance of a SIMD system that utilizes a resume check operation to manage the reactivation of deactivated threads.

Abstract translation: 本公开描述了用于在单个指令，多数据（SIMD）处理系统中选择性地激活恢复检查操作的技术。 描述了一种处理器，其被配置为基于指示是否对该指令执行恢复检查操作的指令中的信息选择性地启用或禁用特定指令的恢复检查操作。 还描述了一种编译器，其被配置为生成编译代码，其在被执行时导致对特定指令选择性地启用或禁用恢复检查操作。 编译代码可以包括一个或多个指令，每个指令指定是否对相应的指令执行恢复检查操作。 本公开的技术可以用于减少利用恢复检查操作来管理停用线程的重新激活的SIMD系统的功耗和/或提高性能。

公开(公告)号：US08305382B2

公开(公告)日：2012-11-06

申请号：US13253473

申请日：2011-10-05

Applicant: Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/00 ,  G06F13/18 ,  G06F15/18

CPC classification number: G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其基于所述多个像素命令线程和所述多个顶点命令线程的相对优先级从所述多个像素或顶点命令线程中选择命令线程。 所选择的命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

公开(公告)号：US20070236495A1

公开(公告)日：2007-10-11

申请号：US11277641

申请日：2006-03-28

Applicant: Andrew Gruber ,  Christopher Brennan

Inventor： Andrew Gruber ,  Christopher Brennan

IPC: G06T15/40

CPC classification number: G06T15/405

Abstract: An apparatus and method for processing pixel depth information eliminates stalling of data in a pixel pipeline, by performing late Z processing for one or more pixels currently in the pixel pipeline and early Z processing for one or more pixels entering the pixel pipeline. The apparatus and method also includes determining whether the late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The apparatus and method also includes solely performing early Z processing for subsequent pixels entering the pixel pipeline responsive to determining that late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The methods and apparatus, facilitates concurrent processing of early and late Z data to avoid flushing portions of the pixel pipeline.

Abstract translation: 用于处理像素深度信息的装置和方法通过对当前在像素流水线中的一个或多个像素执行后期Z处理以及进入像素流水线的一个或多个像素的早期Z处理来消除像素流水线中的数据的停止。 该装置和方法还包括确定当前在像素管线中的一个或多个像素的延迟Z处理是否已经完成。 该装置和方法还包括单独执行对进入像素流水线的后续像素的早期Z处理，以响应于确定当前在像素管线中的一个或多个像素的后期Z处理已经完成。 该方法和装置有助于早期和晚期Z数据的并发处理，以避免冲洗像素管道的部分。

公开(公告)号：US20050154864A1

公开(公告)日：2005-07-14

申请号：US10756853

申请日：2004-01-14

Applicant: Norman Rubin ,  Andrew Gruber

Inventor： Norman Rubin ,  Andrew Gruber

IPC: G06F9/00 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/325 ,  G06F9/30072 ,  G06F9/3885

Abstract: A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further includes a first memory device storing a plurality of instructions wherein each of the plurality of instructions includes a plurality of extra bits. The processor is operative to execute the instructions based on the extra bits and in conjunction with a context bit. The method and apparatus further includes a second memory device, such as a general purpose register operably coupled to the processor, the second memory device receiving an incrementing counter instruction upon the execution of one of the plurality of instructions. As such, the method and apparatus allows for nested control flow through a single context bit in conjunction with instructions having a plurality of extra bits.

Abstract translation: 用于嵌套控制流的方法和装置包括具有至少一个上下文比特的处理器。 处理器包括用于执行单指令多数据（SIMD）操作的多个算术逻辑单元。 该方法和装置还包括存储多个指令的第一存储器件，其中多个指令中的每一个指令包括多个额外的位。 处理器可操作以基于额外的比特并结合上下文比特来执行指令。 所述方法和装置还包括第二存储器装置，诸如可操作地耦合到处理器的通用寄存器，第二存储器装置在执行多个指令之一时接收递增计数器指令。 因此，该方法和装置允许通过单个上下文比特结合具有多个额外比特的指令来嵌套控制流。

公开(公告)号：US10242481B2

公开(公告)日：2019-03-26

申请号：US13421523

申请日：2012-03-15

Applicant: Andrew Gruber ,  Ravi Somnath Jenkal

Inventor： Andrew Gruber ,  Ravi Somnath Jenkal

IPC: G06T1/00 ,  G06T15/00 ,  G06T11/40

Abstract: In general, techniques are described for visibility-based state updates in graphical processing units (GPUs). A device that renders image data comprising a memory configured to store state data and a GPU may implement the techniques. The GPU may be configured to perform a multi-pass rendering process to render an image from the image data. The GPU determines visibility information for a plurality of objects defined by the image data during a first pass of the multi-pass rendering process. The visibility information indicates whether each of the plurality of objects will be visible in the image rendered from the image data during a second pass of the multi-pass rendering process. The GPU then retrieves the state data from the memory for use by the second pass of the multi-pass rendering process in rendering the plurality of objects of the image data based on the visibility information.

公开(公告)号：US10002021B2

公开(公告)日：2018-06-19

申请号：US13554805

申请日：2012-07-20

Applicant: Eduardus A Metz ,  Nigel Terence Poole ,  Colin Christopher Sharp ,  Andrew Gruber

Inventor： Eduardus A Metz ,  Nigel Terence Poole ,  Colin Christopher Sharp ,  Andrew Gruber

IPC: G06T1/20 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/4806 ,  G06F9/461 ,  G06F9/4812 ,  G06T1/20

Abstract: This disclosure is directed to deferred preemption techniques for scheduling graphics processing unit (GPU) command streams for execution on a GPU. A host CPU is described that is configured to control a GPU to perform deferred-preemption scheduling. For example, a host CPU may select one or more locations in a GPU command stream as being one or more locations at which preemption is allowed to occur in response to receiving a preemption notification, and may place one or more tokens in the GPU command stream based on the selected one or more locations. The tokens may indicate to the GPU that preemption is allowed to occur at the selected one or more locations. This disclosure further describes a GPU configured to preempt execution of a GPU command stream based on one or more tokens placed in a GPU command stream.

公开(公告)号：US09071787B2

公开(公告)日：2015-06-30

申请号：US11759633

申请日：2007-06-07

Applicant: Edward G. Callway ,  David Glen ,  Andrew Gruber ,  Gaurav Arora ,  Philip Swan

Inventor： Edward G. Callway ,  David Glen ,  Andrew Gruber ,  Gaurav Arora ,  Philip Swan

IPC: H04N5/66 ,  H04N5/44 ,  G09G5/00 ,  H04N21/41 ,  H04N21/4363

CPC classification number: H04N5/44 ,  G09G5/005 ,  G09G5/006 ,  G09G2320/08 ,  G09G2370/042 ,  H04N21/4122 ,  H04N21/4363

Abstract: In general, in an aspect, the invention provides a multimedia entertainment system including a communication link, a video source coupled to the communication link and configured to produce a video signal and provide the video signal to the communication link, a video display coupled to the communication link and configured to receive the video signal from the video source via the communication link, and to provide dynamic display characteristic information indicative of a display capability of the video display to the video source via the communication link, wherein the video source is configured to receive the dynamic display characteristic information and to produce the video signal as a function of the dynamic display characteristic information, and wherein the video display is configured to display a video image in accordance with the video signal provided by the video source.

Abstract translation: 通常，在一方面，本发明提供了一种多媒体娱乐系统，包括通信链路，耦合到通信链路的视频源，并且被配置为产生视频信号并将视频信号提供给通信链路，视频显示器耦合到 通信链路，并且被配置为经由通信链路从视频源接收视频信号，并且经由通信链路向视频源提供指示视频显示的显示能力的动态显示特性信息，其中视频源被配置为 接收动态显示特性信息并产生作为动态显示特性信息的函数的视频信号，并且其中视频显示被配置为根据由视频源提供的视频信号显示视频图像。