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公开(公告)号：US20070222787A1
公开(公告)日：2007-09-27
申请号：US11746453
申请日：2007-05-09
Applicant: Laurent Lefebvre , Andrew Gruber , Stephen Morein
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
IPC: G06T1/00
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其基于所述多个像素命令线程和所述多个顶点命令线程的相对优先级从所述多个像素或顶点命令线程中选择命令线程。 所选择的命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。
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公开(公告)号：US20070222786A1
公开(公告)日：2007-09-27
申请号：US11746446
申请日：2007-05-09
Applicant: Laurent Lefebvre , Andrew Gruber , Stephen Morein
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
IPC: G06T1/00
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其从所述多个像素命令线程中选择像素命令线程，以及从所述多个顶点命令线程中选择顶点命令线程。 仲裁器还从先前选择的像素命令线程和顶点命令线程中选择命令线程，该命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。
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公开(公告)号：US07239322B2
公开(公告)日：2007-07-03
申请号：US10673761
申请日：2003-09-29
Applicant: Laurent Lefebvre , Andrew Gruber , Stephen Morein
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation station such that the arbiter retrieves a first command thread of the plurality of command threads stored therein such that the arbiter receives the command thread and thereupon provides the command thread to a command processing engine. The system and method further includes the command processing engine coupled to receive the first command thread from the arbiter such that the command processor may perform at least one processing command from the command thread. Whereupon, a command processing engine provides the first command thread back to the associated reservation station.
Abstract translation: 本发明包括一种多线程图形处理系统及其方法，该系统包括具有存储在其中的多个命令线程的保留站。 该系统和方法还包括可操作地耦合到保留站的仲裁器，使得仲裁器检索存储在其中的多个命令线程的第一命令线程，使得仲裁器接收命令线程，并且随后向命令处理引擎提供命令线程 。 该系统和方法还包括命令处理引擎，其被耦合以从仲裁器接收第一命令线程，使得命令处理器可以从命令线程执行至少一个处理命令。 因此，命令处理引擎将第一命令线程提供给相关联的保留站。
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公开(公告)号：US08305382B2
公开(公告)日：2012-11-06
申请号：US13253473
申请日：2011-10-05
Applicant: Laurent Lefebvre , Andrew Gruber , Stephen Morein
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其基于所述多个像素命令线程和所述多个顶点命令线程的相对优先级从所述多个像素或顶点命令线程中选择命令线程。 所选择的命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。
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公开(公告)号：US20050210172A1
公开(公告)日：2005-09-22
申请号：US10791519
申请日：2004-03-02
Applicant: Andrew Gruber , Stephen Morein
Inventor： Andrew Gruber , Stephen Morein
Abstract: A method and apparatus for processing real time command information includes a real time event engine that monitors event signals. A real time event detector within the real time event engine detects when the real time event occurs. Thereupon, real time event commands within a real time event command buffer are fetched and consumed by the command processor in response to the occurrence of the real time event. The real time event detector contains a plurality of control registers, which contain an event selector register, a real time command buffer point register, and a real time command buffer length register. A driver may program the registers, whereupon a singe real time event detector may be used in conjunction with a plurality of real time event command buffers.
Abstract translation: 用于处理实时命令信息的方法和装置包括监视事件信号的实时事件引擎。 实时事件引擎中的实时事件检测器检测何时发生实时事件。 因此，响应于实时事件的发生，由命令处理器获取并消耗实时事件命令缓冲器内的实时事件命令。 实时事件检测器包含多个控制寄存器，其包含事件选择器寄存器，实时命令缓冲器点寄存器和实时命令缓冲器长度寄存器。 驱动器可以对寄存器进行编程，因此可以结合多个实时事件命令缓冲器使用单个实时事件检测器。
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Patent Agency Ranking
公开(公告)号：US08072461B2
公开(公告)日：2011-12-06
申请号：US12718613
申请日：2010-03-05
Applicant: Laurent Lefebvre , Andrew Gruber , Stephen Morein
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其基于所述多个像素命令线程和所述多个顶点命令线程的相对优先级从所述多个像素或顶点命令线程中选择命令线程。 所选择的命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。
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公开(公告)号：US20070222785A1
公开(公告)日：2007-09-27
申请号：US11746427
申请日：2007-05-09
Applicant: Laurent Lefebvre , Andrew Gruber , Stephen Morein
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
IPC: G06T1/00
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: A graphics processing system comprises a command processing engine capable of processing pixel command threads and vertex command threads. The command processing engine is coupled to both a renderer and a scan converter. Upon completing processing of a command thread, which may comprise a pixel command thread or a vertex command thread, the command engine provides the command thread to either the renderer or the scan converter.
Abstract translation: 图形处理系统包括能够处理像素命令线程和顶点命令线程的命令处理引擎。 命令处理引擎与渲染器和扫描转换器耦合。 在完成可以包括像素命令线程或顶点命令线程的命令线程的处理之后，命令引擎将命令线程提供给渲染器或扫描转换器。
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公开(公告)号：US20050068325A1
公开(公告)日：2005-03-31
申请号：US10673761
申请日：2003-09-29
Applicant: Laurent Lefebvre , Andrew Gruber , Stephen Morein
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation station such that the arbiter retrieves a first command thread of the plurality of command threads stored therein such that the arbiter receives the command thread and thereupon provides the command thread to a command processing engine. The system and method further includes the command processing engine coupled to receive the first command thread from the arbiter such that the command processor may perform at least one processing command from the command thread. Whereupon, a command processing engine provides the first command thread back to the associated reservation station.
Abstract translation: 本发明包括一种多线程图形处理系统及其方法，该系统包括具有存储在其中的多个命令线程的保留站。 该系统和方法还包括可操作地耦合到保留站的仲裁器，使得仲裁器检索存储在其中的多个命令线程的第一命令线程，使得仲裁器接收命令线程，并且随后向命令处理引擎提供命令线程 。 该系统和方法还包括命令处理引擎，其被耦合以从仲裁器接收第一命令线程，使得命令处理器可以从命令线程执行至少一个处理命令。 因此，命令处理引擎将第一命令线程提供给相关联的保留站。
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公开(公告)号：US08429356B2
公开(公告)日：2013-04-23
申请号：US11359809
申请日：2006-02-22
Applicant: Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
Inventor： Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
IPC: G06F13/00
CPC classification number: G06F12/00 , G06F13/4234 , G06F13/4243 , G11C7/02 , G11C7/1006 , G11C7/1078 , G11C7/1096
Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.
Abstract translation: 描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。 实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。 不使用专用的掩码引脚或专用掩码线。 在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。 在一个实施例中，掩模数据作为写入命令的一部分被发送。
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公开(公告)号：US07869525B2
公开(公告)日：2011-01-11
申请号：US11357291
申请日：2006-02-17
Applicant: Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
Inventor： Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
IPC: H04B3/00
CPC classification number: H04L25/4915 , H03L7/07 , H03L7/0805 , H03L7/0814 , H04L7/0004 , H04L7/0008 , H04L7/0037 , H04L7/0337
Abstract: A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.
Abstract translation: 描述了动态总线反演（DBI）方法和系统。 在各种实施例中，发射机通过多比特高速总线向接收机发送数据。 在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。 如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。 在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。 接收器接收并解码DBI信号，作为响应，对接收到的数据进行适当的解码。
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