公开(公告)号：US06624771B2

公开(公告)日：2003-09-23

申请号：US10145390

申请日：2002-05-14

Applicant: Ankur Bal

Inventor： Ankur Bal

IPC: H03M700

CPC classification number: H03K19/17728

Abstract: A look-up table circuit includes address decoder circuitry that includes circuitry for utilizing the address decoder circuitry for producing secondary functions concurrently with operation of the address decoding operations. This eliminates or reduces additional circuitry required for generating the secondary functions.

Abstract translation: 查找表电路包括地址解码器电路，其包括用于利用地址解码器电路与地址解码操作的操作同时产生辅助功能的电路。 这消除或减少了生成次要功能所需的附加电路。

公开(公告)号：US09015219B2

公开(公告)日：2015-04-21

申请号：US13468924

申请日：2012-05-10

Applicant: Ankur Bal ,  Anupam Jain ,  Neha Bhargava

Inventor： Ankur Bal ,  Anupam Jain ,  Neha Bhargava

IPC: G06F17/10 ,  H03H17/06

CPC classification number: H03H17/0664

Abstract: A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.

Abstract translation: 信号处理器包括一个或多个存储体，其中每个存储体存储滤波器系数; 和一个或多个系数多路复用器单元; 每个系数多路复用器单元与存储器组相关联，并且基于所接收的输入采样的数量来检索滤波器系数。 处理器包括一个或多个乘法和累积（MAC）单元，每个MAC单元与系数多路复用器单元相关联，并且确定所检索的滤波器系数与输入采样的乘积; 检索存储在相关联寄存器中的先前值; 计算以前的值和乘积的总和; 并将求和存储在相关联的寄存器中。 处理器包括输出多路复用器单元，用于选择寄存器，并将存储在寄存器中的值提供为输出。

公开(公告)号：US08731214B2

公开(公告)日：2014-05-20

申请号：US12766210

申请日：2010-04-23

Applicant: Ankur Bal ,  Anupam Jain ,  Rakhel Kumar Parida

Inventor： Ankur Bal ,  Anupam Jain ,  Rakhel Kumar Parida

IPC: H04B15/00

CPC classification number: G10K11/002 ,  G10L21/0208 ,  G10L21/0232 ,  H04L5/0008 ,  H04L25/03159 ,  H04L27/2649 ,  H04L2025/03414

Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.

Abstract translation: 用于噪声去除的系统耦合到提供数字信号的信号单元。 噪声去除系统包括：将数字信号变换为f数字信号的变换模块，基于阈值分布的f数字信号产生无噪声信号的阈值滤波器;以及信号合成器，用于向 并将无噪声信号变换为输出信号。

公开(公告)号：US06888374B2

公开(公告)日：2005-05-03

申请号：US10464420

申请日：2003-06-17

Applicant: Ankur Bal

Inventor： Ankur Bal

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17796

Abstract: An FPCA includes a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxes at the periphery for maintaining constant routing channel width.

Abstract translation: FPCA包括用于外围路由的方​​案，其通过并入正交对称偏转的相等长度的外围路由线来提供包括外围在内的整个区域的对称路由。 对称的外围路由线路连接到外围的交换机和连接盒，以保持不断的路由信道宽度。

公开(公告)号：US06748577B2

公开(公告)日：2004-06-08

申请号：US10186314

申请日：2002-06-28

Applicant: Ankur Bal

Inventor： Ankur Bal

IPC: G06F1750

CPC classification number: H03K19/1776 ,  H03K19/17736 ,  H03K19/17744

Abstract: A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.

Abstract translation: 提供了一种用于简化现场可编程门阵列（FPGA）中的可编程存储器到逻辑接口的系统。 可以使用接口来隔离来自随机存取存储器（RAM）地址线，数据线和控制线的可编程逻辑块（PLB）的通用路由架构。 FPGA的PLB和输入输出资源使用专用直接互连访问嵌入式存储器（或RAM）。 这些直接互连中的某些可能来自RAM附近的PLB。 剩余部分在输入 - 输出（IO）焊盘/路由和RAM块之间运行。 还提供总线路由架构以组合存储器以模拟较大的RAM块。 该总线路由提供RAM块之间的互连，并与PLB路由资源隔离。

公开(公告)号：US11336194B1

公开(公告)日：2022-05-17

申请号：US17221905

申请日：2021-04-05

Applicant: Vikram Singh ,  Ankur Bal ,  Vineet Mehta ,  Jitender Singh

Inventor： Vikram Singh ,  Ankur Bal ,  Vineet Mehta ,  Jitender Singh

IPC: H02M7/42 ,  H02M3/335 ,  H02M1/12

Abstract: Disclosed herein is a DC-AC converter, in accordance with some embodiments. Accordingly, the DC-AC converter comprises a transformer, a pulse generator, a pulse modulator, a switching element, and an analog low pass filtering stage. Further, the pulse generator is configured for generating pulses characterized by a pulse frequency. Further, the pulse modulator is configured for generating a pulse density modulated signal based on modulating the pulses using a sine wave signal of a fundamental frequency. Further, the switching element is connected in series with a primary winding of the transformer. Further, the switching element is configured to be switched between an on state and an off state based on the pulse density modulated signal. Further, the analog low pass filtering stage is configured for generating an AC voltage of the fundamental frequency based on attenuating higher frequency components of an unfiltered AC voltage at a secondary winding of the transformer.

公开(公告)号：US08803718B2

公开(公告)日：2014-08-12

申请号：US13422833

申请日：2012-03-16

Applicant: Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

Inventor： Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

IPC: H03M1/66 ,  H03M7/14 ,  H03M1/06 ,  H03M7/12 ,  H03M1/74

CPC classification number: H03M7/12 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M7/14

Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b−1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

Abstract translation: 用于将b位二进制输入代码转换为（2b-1）位数字输出代码的爬行码生成器中实现动态元素匹配（DEM）方案。 随机生成器确定每个转换步骤一个方向。 计算当前和前一个二进制输入之间的十进制差值。 新的爬行输出代码基于先前的爬行输出代码，方向和小数差来确定。 DEM方案用于数模转换器，使得爬行输出码切换输出模拟信号的数模转换元件，然后将模拟信号相加为最终的模拟信号。

公开(公告)号：US07856467B2

公开(公告)日：2010-12-21

申请号：US11324019

申请日：2005-12-29

Applicant: Parvesh Swami ,  Ankur Bal

Inventor： Parvesh Swami ,  Ankur Bal

IPC: G06F7/52

CPC classification number: G06F7/523 ,  G06F7/5312

Abstract: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.

Abstract translation: 本发明提供了一种集成电路，其包括能够进行乘法的至少一个可配置逻辑单元，该逻辑单元包括用于添加第一输入和部分乘积的加法装置; 第一多路复用装置，用于在其第一输入处接收所述加法装置的第一输出，在其第二输入处接收所述部分乘积，其选择线由第二输入控制，所述第一多路复用装置提供第一输出; 以及第二多路复用装置，用于在其第一输入处接收所述加法装置的第二输出，在其第二输入处接收所述第二输入，其选择线耦合到所述第二输入，所述第二多路复用装置提供第二输出。

公开(公告)号：US20100121897A1

公开(公告)日：2010-05-13

申请号：US12614004

申请日：2009-11-06

Applicant: Ankur Bal ,  Anupam Jain

Inventor： Ankur Bal ,  Anupam Jain

IPC: G06F17/17

CPC classification number: H03H17/0286 ,  H03H17/0671

Abstract: The invention may provide a method and filter block for compensating droop in a frequency response of a signal. The filter block may include a decimator, which decimates a high frequency input signal to a set frequency output signal. The set frequency can be, for example, the Nyquist frequency for the input signal. Further, the filter block may include a droop compensator that compensates the droop in the frequency response of the output signal from the decimator. The droop compensator may be made using recursive filters, as opposed to large tap FIR filters, which may result in less memory consumption and decreased power consumption.

Abstract translation: 本发明可以提供一种用于在信号的频率响应中补偿下降的方法和滤波器块。 滤波器块可以包括抽取器，其将高频输入信号抽取到设定频率输出信号。 设定频率可以是例如输入信号的奈奎斯特频率。 此外，滤波器块可以包括下降补偿器，其补偿来自抽取器的输出信号的频率响应中的下降。 下降补偿器可以使用递归滤波器制造，而不是大抽头FIR滤波器，这可能导致较少的存储器消耗和降低的功耗。

公开(公告)号：US20060195503A1

公开(公告)日：2006-08-31

申请号：US11324019

申请日：2005-12-28

Applicant: Parvesh Swami ,  Ankur Bal

Inventor： Parvesh Swami ,  Ankur Bal

IPC: G06F7/52

CPC classification number: G06F7/523 ,  G06F7/5312

Abstract: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.

Abstract translation: 本发明提供了一种集成电路，其包括能够进行乘法的至少一个可配置逻辑单元，该逻辑单元包括用于添加第一输入和部分乘积的加法装置; 第一多路复用装置，用于在其第一输入处接收所述加法装置的第一输出，在其第二输入处接收所述部分乘积，其选择线由第二输入控制，所述第一多路复用装置提供第一输出; 以及第二多路复用装置，用于在其第一输入处接收所述加法装置的第二输出，在其第二输入处接收所述第二输入，其选择线耦合到所述第二输入，所述第二多路复用装置提供第二输出。