公开(公告)号：US09471378B2

公开(公告)日：2016-10-18

申请号：US14620905

申请日：2015-02-12

Applicant: Apple Inc.

Inventor： Lionel D. Desai ,  Neil G. Crane ,  Damien P. Sorresso ,  Joseph Sokol, Jr.

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52

CPC classification number: G06F9/4881 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/5038 ,  G06F9/528

Abstract: A method for resource management of a data processing system is described herein. According to one embodiment, a token is periodically pushed into a memory usage queue, where the token includes a timestamp indicating time entering the memory usage queue. The memory usage queue stores a plurality of memory page identifiers (IDs) identifying a plurality of memory pages currently allocated to a plurality of programs running within the data processing system. In response to a request to reduce memory usage, a token is popped from the memory usage queue. A timestamp of the popped token is then compared with current time to determine whether a memory usage reduction action should be performed.

公开(公告)号：US09436628B2

公开(公告)日：2016-09-06

申请号：US14503312

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Umesh Suresh Vaishampayan ,  Derek R. Kumar ,  Christopher John Sarcone ,  Russell Alexader Blaine ,  Tejas Arun Bahulkar ,  Shachar Katz ,  Joseph Sokol, Jr. ,  Matthew John Byom

IPC: G06F5/00 ,  G06F13/26 ,  G06F13/10 ,  G05D23/19 ,  G06F1/20

CPC classification number: G06F13/26 ,  G05D23/1917 ,  G06F1/206 ,  G06F13/102 ,  Y02D10/14 ,  Y02D10/16

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling input/output operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilize storage of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first bandwidth range for the low priority process and maintains a second bandwidth range for the high priority process. The device further processes a storage request of the low priority process using the first bandwidth range and processing a storage request of the high priority process using the second bandwidth range.

Abstract translation: 描述了通过选择性地节流设备的输入/输出操作来管理设备的热轮廓的设备的方法和装置。 在示例性实施例中，设备监视设备的热分布，其中设备执行利用设备的存储的多个进程。 另外，多个处理包括高优先级处理和低优先级处理。 如果设备的热分布超过热阈值，则设备会降低低优先级进程的第一带宽范围，并为高优先级进程维护第二带宽范围。 该设备还使用第一带宽范围来处理低优先级进程的存储请求，并使用第二带宽范围来处理高优先级进程的存储请求。

公开(公告)号：US11138346B2

公开(公告)日：2021-10-05

申请号：US16859634

申请日：2020-04-27

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/78 ,  H04L9/08

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US10970203B2

公开(公告)日：2021-04-06

申请号：US16668368

申请日：2019-10-30

Applicant: Apple Inc.

Inventor： Joseph Sokol, Jr.

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/08

Abstract: A method and an apparatus for a memory device including a dynamically updated portion of compressed memory for a virtual memory are described. The memory device can include an uncompressed portion of memory separate from the compressed portion of memory. The virtual memory may be capable of mapping a memory address to the compressed portion of memory. A memory region allocated in the uncompressed portion of memory can be compressed into the compressed portion of memory. As a result, the memory region can become available (e.g. after being compressed) for future allocation requested in the memory device. The compressed portion of memory may be updated to store the compressed memory region. The compressed memory region may be decompressed back to the uncompressed portion in the memory device in response to a request to access data in the compressed memory region.

公开(公告)号：US10671762B2

公开(公告)日：2020-06-02

申请号：US15748893

申请日：2016-08-25

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/78 ,  H04L9/08

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US11714924B2

公开(公告)日：2023-08-01

申请号：US17469591

申请日：2021-09-08

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/78 ,  H04L9/08

CPC classification number: G06F21/72 ,  G06F12/0246 ,  G06F12/1027 ,  G06F12/1408 ,  G06F21/78 ,  H04L9/0861 ,  H04L9/0894 ,  G06F2212/7206 ,  G06F2212/7208 ,  G06F2221/2143 ,  H04L2209/12

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US20200257829A1

公开(公告)日：2020-08-13

申请号：US16859634

申请日：2020-04-27

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/78 ,  G06F12/14 ,  G06F12/1027 ,  G06F12/02

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US09772959B2

公开(公告)日：2017-09-26

申请号：US14292123

申请日：2014-05-30

Applicant: Apple Inc.

Inventor： Russell A. Blaine ,  Kushal Dalmia ,  Joseph Sokol, Jr. ,  Andrew W. Vogan ,  Matthew J. Byom

IPC: G06F13/18 ,  G06F3/06 ,  G06F13/38 ,  G06F9/00

CPC classification number: G06F13/18 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0688 ,  G06F9/00 ,  G06F13/385

Abstract: In one embodiment, input-output (I/O) scheduling system detects and resolves priority inversions by expediting previously dispatched requests to an I/O subsystem. In response to detecting the priority inversion, the system can transmit a command to expedite completion of the blocking I/O request. The pending request can be located within the I/O subsystem and expedited to reduce the pendency period of the request.