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公开(公告)号：US10223822B2
公开(公告)日：2019-03-05
申请号：US15388915
申请日：2016-12-22
Applicant: Apple Inc.
Inventor： Terence M. Potter , Ralph C. Taylor , Richard W. Schreyer , Aaftab A. Munshi , Justin A. Hensley
Abstract: Techniques are disclosed relating to performing mid-render auxiliary compute tasks for graphics processing. In some embodiments, auxiliary compute tasks are performed during a render pass, using at least a portion of a memory context of the render pass, without accessing a shared memory during the render pass. Relative to flushing render data to shared memory to perform compute tasks, this may reduce memory accesses and/or cache thrashing, which may in turn increase performance and/or reduce power consumption.
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公开(公告)号：US20190042312A1
公开(公告)日：2019-02-07
申请号：US15669445
申请日：2017-08-04
Applicant: Apple Inc.
Inventor： Mark D. Earl , Dimitri Tan , Christopher L. Spencer , Jeffrey T. Brady , Ralph C. Taylor , Terence M. Potter
IPC: G06F9/50
Abstract: In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.
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公开(公告)号：US20180182153A1
公开(公告)日：2018-06-28
申请号：US15388915
申请日：2016-12-22
Applicant: Apple Inc.
Inventor： Terence M. Potter , Ralph C. Taylor , Richard W. Schreyer , Aaftab A. Munshi , Justin A. Hensley
CPC classification number: G06T15/005 , G06F9/5038 , G06F9/5066 , G06F9/544 , G06T1/20 , G06T15/80 , Y02D10/22 , Y02D10/36
Abstract: Techniques are disclosed relating to performing mid-render auxiliary compute tasks for graphics processing. In some embodiments, auxiliary compute tasks are performed during a render pass, using at least a portion of a memory context of the render pass, without accessing a shared memory during the render pass. Relative to flushing render data to shared memory to perform compute tasks, this may reduce memory accesses and/or cache thrashing, which may in turn increase performance and/or reduce power consumption.
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公开(公告)号：US20180173560A1
公开(公告)日：2018-06-21
申请号：US15386570
申请日：2016-12-21
Applicant: Apple Inc.
Inventor： Gokhan Avkarogullari , Terence M. Potter , Benjiman L. Goodman , Ralph C. Taylor , Kutty Banerjee
CPC classification number: G06F9/4818 , G06F9/505 , G06F2209/5021
Abstract: In various embodiments, hardware resources of a processing circuit may be allocated to a plurality of processes based on priorities of the processes. A hardware resource utilization sensor may detect a current utilization of the hardware resources by a process. A utilization accumulation circuit may determine a utilization of the hardware resources by the process over a particular amount of time. A target utilization of the hardware resources for the process may be determined based on the utilization of the hardware resources over the particular amount of time. A comparator circuit may compare the current utilization to the target utilization. A process priority adjustment circuit may adjust a priority of the process based on the comparison. Based on the adjusted priority, a different amount of hardware resources may be allocated to the processes.
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Patent Agency Ranking
公开(公告)号：US12165251B1
公开(公告)日：2024-12-10
申请号：US18054612
申请日：2022-11-11
Applicant: Apple Inc.
Inventor： Michael A. Mang , Jason D. Carroll , Jingfei Kong , Ralph C. Taylor
Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry, shader circuitry configured to execute graphics programs, including mesh shaders that store output data in the buffer circuitry, and primitive processing circuitry configured to read data from buffer circuitry and process the data, including to cull primitives that are not visible in a graphics frame. Vertex control circuitry may receive: first signaling from the primitive processing circuitry that indicates whether the primitive processing circuitry is waiting for data from the buffer circuitry and second signaling from the shader circuitry that indicates whether the shader circuitry is blocked waiting for allocation in the buffer circuitry. The vertex control circuitry may adjust distribution of mesh shader work to the shader circuitry based on the first signaling and the second signaling.
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公开(公告)号：US11829298B2
公开(公告)日：2023-11-28
申请号：US16804128
申请日：2020-02-28
Applicant: Apple Inc.
Inventor： Justin A. Hensley , Karl D. Mann , Yoong Chert Foo , Terence M. Potter , Frank W. Liljeros , Ralph C. Taylor
IPC: G06F12/1018 , G06F12/084 , G06F30/392
CPC classification number: G06F12/1018 , G06F12/084 , G06F30/392 , G06F2212/622 , G06F2212/651
Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.
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公开(公告)号：US11113788B2
公开(公告)日：2021-09-07
申请号：US17001007
申请日：2020-08-24
Applicant: Apple Inc.
Inventor： Justin A. Hensley , Karl D. Mann , Ralph C. Taylor , Randall R. Rauwendaal , Jonathan M. Redshaw
Abstract: Techniques are disclosed relating to rendering graphics objects. In some embodiments, a graphics unit is configured to transform graphics objects from a virtual space into a second space according to different transformation parameters for different portions of the second space. This may result in sampling different portions of the virtual space at different sample rates, which may reduce the number of samples required in various stages of the rendering process. In the disclosed techniques, transformation may occur prior to rasterization and shading, which may further reduce computation and power consumption in a graphics unit, improve image quality as displayed to a user, and/or reduce bandwidth usage or latency of video content on a network. In some embodiments, a transformed image may be viewed through a distortion-compensating lens or resampled prior to display.
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公开(公告)号：US10990445B2
公开(公告)日：2021-04-27
申请号：US15669445
申请日：2017-08-04
Applicant: Apple Inc.
Inventor： Mark D. Earl , Dimitri Tan , Christopher L. Spencer , Jeffrey T. Brady , Ralph C. Taylor , Terence M. Potter
Abstract: In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.
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公开(公告)号：US20190102865A1
公开(公告)日：2019-04-04
申请号：US16130265
申请日：2018-09-13
Applicant: Apple Inc.
Inventor： Justin A. Hensley , Karl D. Mann , Ralph C. Taylor , Randall R. Rauwendaal , Jonathan M. Redshaw
Abstract: Techniques are disclosed relating to rendering graphics objects. In some embodiments, a graphics unit is configured to transform graphics objects from a virtual space into a second space according to different transformation parameters for different portions of the second space. This may result in sampling different portions of the virtual space at different sample rates, which may reduce the number of samples required in various stages of the rendering process. In the disclosed techniques, transformation may occur prior to rasterization and shading, which may further reduce computation and power consumption in a graphics unit, improve image quality as displayed to a user, and/or reduce bandwidth usage or latency of video content on a network. In some embodiments, a transformed image may be viewed through a distortion-compensating lens or resampled prior to display.
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