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公开(公告)号：US10853907B2
公开(公告)日：2020-12-01
申请号：US16511742
申请日：2019-07-15
Applicant: Apple Inc.
Inventor： Tatsuya Iwamoto , Kutty Banerjee , Rohan Sanjeev Patil
Abstract: Systems, methods, and computer readable media to improve task switching operations in a graphics processing unit (GPU) are described. As disclosed herein, the clock rate (and voltages) of a GPU's operating environment may be altered so that a low priority task may be rapidly run to a task switch boundary (or completion) so that a higher priority task may begin execution. In some embodiments, only the GPU's operating clock (and voltage) is increased during the task switch operation. In other embodiments, the clock rate (voltages) of supporting components may also be increased. For example, the operating clock for the GPU's supporting memory, memory controller or memory fabric may also be increased. Once the lower priority task has been swapped out, one or more of the clocks (and voltages) increased during the switch operation could be subsequently decreased, though not necessarily to their pre-switch rates.
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公开(公告)号：US10373287B2
公开(公告)日：2019-08-06
申请号：US15680885
申请日：2017-08-18
Applicant: Apple Inc.
Inventor： Tatsuya Iwamoto , Kutty Banerjee , Rohan Sanjeev Patil
Abstract: Systems, methods, and computer readable media to improve task switching operations in a graphics processing unit (GPU) are described. As disclosed herein, the clock rate (and voltages) of a GPU's operating environment may be altered so that a low priority task may be rapidly run to a task switch boundary (or completion) so that a higher priority task may begin execution. In some embodiments, only the GPU's operating clock (and voltage) is increased during the task switch operation. In other embodiments, the clock rate (voltages) of supporting components may also be increased. For example, the operating clock for the GPU's supporting memory, memory controller or memory fabric may also be increased. Once the lower priority task has been swapped out, one or more of the clocks (and voltages) increased during the switch operation could be subsequently decreased, though not necessarily to their pre-switch rates.
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公开(公告)号：US20190057484A1
公开(公告)日：2019-02-21
申请号：US15680885
申请日：2017-08-18
Applicant: Apple Inc.
Inventor： Tatsuya Iwamoto , Kutty Banerjee , Rohan Sanjeev Patil
CPC classification number: G06T1/20 , G06F9/485 , G06F9/4881
Abstract: Systems, methods, and computer readable media to improve task switching operations in a graphics processing unit (GPU) are described. As disclosed herein, the clock rate (and voltages) of a GPU's operating environment may be altered so that a low priority task may be rapidly run to a task switch boundary (or completion) so that a higher priority task may begin execution. In some embodiments, only the GPU's operating clock (and voltage) is increased during the task switch operation. In other embodiments, the clock rate (voltages) of supporting components may also be increased. For example, the operating clock for the GPU's supporting memory, memory controller or memory fabric may also be increased. Once the lower priority task has been swapped out, one or more of the clocks (and voltages) increased during the switch operation could be subsequently decreased, though not necessarily to their pre-switch rates.
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公开(公告)号：US20220269619A1
公开(公告)日：2022-08-25
申请号：US17654726
申请日：2022-03-14
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/1027
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
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Patent Agency Ranking
公开(公告)号：US10719970B2
公开(公告)日：2020-07-21
申请号：US15864833
申请日：2018-01-08
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Rohan Sanjeev Patil , Pratik Chandresh Shah , Gokhan Avkarogullari , Tatsuya Iwamoto
Abstract: One disclosed embodiment includes a method of scheduling graphics commands for processing. A plurality of micro-commands is generated based on one or more graphics commands obtained from a central processing unit. The dependency between the one or more graphics commands is then determined and an execution graph is generated based on the determined dependency. Each micro-command in the execution graph is connected by an edge to the other micro-commands that it depends on. A wait count is defined for each micro-command of the execution graph, where the wait count indicates the number of micro-commands that the each particular micro-command depends on. One or more micro-commands with a wait count of zero are transmitted to a ready queue for processing.
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公开(公告)号：US10678553B2
公开(公告)日：2020-06-09
申请号：US15961086
申请日：2018-04-24
Applicant: Apple Inc.
Inventor： Rohan Sanjeev Patil , Gokhan Avkarogullari , Tatsuya Iwamoto
IPC: G06F15/177 , G06F9/00 , G06F9/4401 , G06F1/3206 , G06T15/00 , G06F9/50 , G06T1/20
Abstract: One disclosed embodiment includes a method of graphics processing. The method includes receiving an indication to update a current frame on a display. A plurality of graphics command are determined to be associated with a next frame that replaces the current frame. A power-up command is generated based on the received indication, configured to cause GPU hardware to begin an initialization operation. The central processing unit processes the plurality of graphics command. Prior to completely process the plurality of graphics command, a power-up command is sent to a GPU firmware. The GPU firmware initializes the GPU hardware based on the power-up command. The processed plurality of graphics command is also transmitted to the GPU hardware. The GPU hardware executes the processed plurality of graphics command to render the next frame on the display.
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公开(公告)号：US20190340723A1
公开(公告)日：2019-11-07
申请号：US16511742
申请日：2019-07-15
Applicant: Apple Inc.
Inventor： Tatsuya Iwamoto , Kutty Banerjee , Rohan Sanjeev Patil
Abstract: Systems, methods, and computer readable media to improve task switching operations in a graphics processing unit (GPU) are described. As disclosed herein, the clock rate (and voltages) of a GPU's operating environment may be altered so that a low priority task may be rapidly run to a task switch boundary (or completion) so that a higher priority task may begin execution. In some embodiments, only the GPU's operating clock (and voltage) is increased during the task switch operation. In other embodiments, the clock rate (voltages) of supporting components may also be increased. For example, the operating clock for the GPU's supporting memory, memory controller or memory fabric may also be increased. Once the lower priority task has been swapped out, one or more of the clocks (and voltages) increased during the switch operation could be subsequently decreased, though not necessarily to their pre-switch rates.
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公开(公告)号：US20180349146A1
公开(公告)日：2018-12-06
申请号：US15615412
申请日：2017-06-06
Applicant: Apple Inc.
Inventor： Tatsuya Iwamoto , Kutty Banerjee , Benjiman L. Goodman , Terence M. Potter
Abstract: In general, techniques are disclosed for tracking and allocating graphics processor hardware over specified periods of time. More particularly, hardware sensors may be used to determine the utilization of graphics processor hardware after each of a number of specified intervals (referred to as “sample intervals”). The utilization values so captured may be combined after a first number of sample intervals (the combined interval referred to as an “epoch interval”) and used to determine a normalized utilization of the graphic processor's hardware resources. Normalized epoch utilization values have been adjusted to account for resources used by concurrently executing processes. In some embodiments, a lower priority process that obtains and fails to release resources that should be allocated to one or more higher priority processes may be detected, paused, and its hardware resources given to the higher priority processes.
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公开(公告)号：US20160358305A1
公开(公告)日：2016-12-08
申请号：US14851629
申请日：2015-09-11
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Eric O. Sunalp , Tatsuya Iwamoto
IPC: G06T1/20
CPC classification number: G06T1/20 , G06F9/5044 , G06F9/505 , G06F2209/5021 , G06T2200/28
Abstract: Embodiments are directed toward systems and methods for scheduling resources of a graphics processing unit that determine, for a number of applications having commands to be issued to the GPU, a static priority level and a dynamic priority level of each application, work iteratively across static priority levels until a resource budget of the GPU is consumed, and starting with a highest static priority identify the applications in a present static priority level, assign a processing budget of the GPU to each of the applications in the present static priority level according to their dynamic priority levels, and admit to a queue commands from the applications in the present static priority level according to their processing budgets, and release the queue to the GPU.
Abstract translation: 实施例针对用于调度图形处理单元的资源的系统和方法，其针对具有要发布给GPU的命令的多个应用程序确定每个应用的静态优先级和动态优先级，跨静态优先级 直到GPU的资源预算被消耗，并以最高的静态优先级开始以当前静态优先级级别识别应用，根据它们的动态向当前静态优先级中的每一个应用分配GPU的处理预算 优先级，并根据其处理预算承认来自当前静态优先级的应用程序的命令，并将队列释放到GPU。
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