公开(公告)号：US20230005908A1

公开(公告)日：2023-01-05

申请号：US17930188

申请日：2022-09-07

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F30/398

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

公开(公告)号：US10700065B2

公开(公告)日：2020-06-30

申请号：US16156461

申请日：2018-10-10

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F30/398

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

公开(公告)号：US20240105727A1

公开(公告)日：2024-03-28

申请号：US18448746

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Xin Miao ,  Praveen Raghavan ,  Thomas Hoffmann ,  Saurabh P. Sinha

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11851 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include cells that form inverter devices, NAND devices, and MUX (multiplexer) devices. The disclosed cells include two or four vertical transistors with various connections made to the transistors that include either connected gate logic for inverter and NAND devices or disconnected gate logic for MUX devices.

公开(公告)号：US20240105617A1

公开(公告)日：2024-03-28

申请号：US18448715

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Xin Miao ,  Praveen Raghavan ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/42376 ,  H01L29/7827

Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include a building block cell with a metal contact layer between the backside metal routing and the vertical transistors. Various connections can be made within the building block cell to form more complex structures such as, but not limited to, inverter devices, NAND devices, and MUX (multiplexer) devices.

公开(公告)号：US20240047353A1

公开(公告)日：2024-02-08

申请号：US18488561

申请日：2023-10-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/58

CPC classification number: H01L23/528 ,  H01L23/5386 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/0652 ,  H01L23/585 ,  H01L22/20

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US11469226B2

公开(公告)日：2022-10-11

申请号：US16913770

申请日：2020-06-26

Applicant: Apple Inc.

Inventor： Emre Alptekin ,  Thomas Hoffmann

IPC: H01L27/088 ,  H01L27/02 ,  G06F30/398

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.