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公开(公告)号:US20250053667A1
公开(公告)日:2025-02-13
申请号:US18774305
申请日:2024-07-16
Applicant: Apple Inc.
Inventor: Timothy R. Paaske , Mitchell D. Adler , Conrad Sauerwald , Fabrice L. Gautier , Shu-Yi Yu
Abstract: In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.
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公开(公告)号:US12079350B2
公开(公告)日:2024-09-03
申请号:US18301860
申请日:2023-04-17
Applicant: Apple Inc.
Inventor: Timothy R. Paaske , Mitchell D. Adler , Conrad Sauerwald , Fabrice L. Gautier , Shu-Yi Yu
CPC classification number: G06F21/602 , G06F21/6218 , G06F21/71 , G09C1/00 , H04L9/0866 , H04L9/0877 , H04L9/30 , H04L9/3231 , G06F21/32 , H04L2209/125
Abstract: In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.
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公开(公告)号:US11818681B2
公开(公告)日:2023-11-14
申请号:US17582785
申请日:2022-01-24
Applicant: Apple Inc.
Inventor: Jerrold V. Hauck , Alejandro J. Marquez , Timothy R. Paaske , Indranil S. Sen , Herve Sibert , Yannick L. Sierra , Raman S. Thiara
IPC: H04W64/00 , H04W12/03 , H04W12/033 , H04W12/041 , H04W12/062 , H04W12/63 , H04W12/065 , H04W12/069 , H04W12/0431 , H04W12/0433 , H04W12/0471 , H04W76/10 , H04L9/32 , H04L9/40 , H04W12/02 , H04W12/04 , H04W12/06 , H04W12/47 , H04W12/33 , H04W4/80
CPC classification number: H04W64/00 , H04L9/3273 , H04L63/061 , H04L63/0869 , H04W12/02 , H04W12/03 , H04W12/033 , H04W12/04 , H04W12/041 , H04W12/0431 , H04W12/0433 , H04W12/0471 , H04W12/06 , H04W12/062 , H04W12/065 , H04W12/069 , H04W12/63 , H04W76/10 , H04L63/0492 , H04W4/80 , H04W12/33 , H04W12/47
Abstract: A secure ranging system can use a secure processing system to deliver one or more ranging keys to a ranging radio on a device, and the ranging radio can derive locally at the system ranging codes based on the ranging keys. A deterministic random number generator can derive the ranging codes using the ranging key and one or more session parameters, and each device (e.g. a cellular telephone and another device) can independently derive the ranging codes and derive them contemporaneously with their use in ranging operations.
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公开(公告)号:US11374967B2
公开(公告)日:2022-06-28
申请号:US16276504
申请日:2019-02-14
Applicant: Apple Inc.
Inventor: Zhimin Chen , Timothy R. Paaske , Gilbert H. Herbeck
Abstract: A system and method for detecting replay attacks on secure data are disclosed. A system on a chip (SOC) includes a security processor. Blocks of data corresponding to sensitive information are stored in off-chip memory. The security processor uses an integrity data structure, such as an integrity tree, for the blocks. The intermediate nodes of the integrity tree use nonces which have been generated independent of any value within a corresponding block. By using only the nonces to generate tags in the root at the top layer stored in on-chip memory and the nodes of the intermediate layers stored in off-chip memory, an amount of storage used is reduced for supporting the integrity tree. When the security processor detects events which create access requests for one or more blocks, the security processor uses the integrity tree to verify a replay attack has not occurred and corrupted data.
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公开(公告)号:US11263306B2
公开(公告)日:2022-03-01
申请号:US16927934
申请日:2020-07-13
Applicant: Apple Inc.
Inventor: Timothy R. Paaske , Weihua Mao , Shu-Yi Yu
Abstract: An apparatus, a method, and a system are presented in which the apparatus includes an interface control circuit that may be configured to receive a message including a cryptographic keyword and a policy value. The policy value may include one or more data bits indicative of one or more policies that define allowable usage of the cryptographic keyword. The apparatus also includes a security circuit that may be configured to extract the cryptographic keyword and the policy value from the message, and to apply at least one policy of the one or more policies to usage of the cryptographic keyword in response to a determination that an authentication of the message succeeded.
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公开(公告)号:US20180349608A1
公开(公告)日:2018-12-06
申请号:US15721365
申请日:2017-09-29
Applicant: Apple Inc.
Inventor: Joshua P. de Cesare , Timothy R. Paaske , Xeno S. Kovah , Nikolaj Schlej , Jeffrey R. Wilcox , Ezekiel T. Runyon , Hardik K. Doshi , Kevin H. Alderfer , Corey T. Kallenberg
CPC classification number: G06F21/575
Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.
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公开(公告)号:US09740645B2
公开(公告)日:2017-08-22
申请号:US14691244
申请日:2015-04-20
Applicant: Apple Inc.
Inventor: Michael W. Murphy , Joshua P. de Cesare , Timothy R. Paaske
CPC classification number: G06F13/24 , G06F1/3253 , Y02D10/151
Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.
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公开(公告)号:US20170024559A1
公开(公告)日:2017-01-26
申请号:US14807609
申请日:2015-07-23
Applicant: Apple Inc.
Inventor: Gregory D. Hughes , Conrado Blasco , Gerard R. Williams, III , Jacques Anthony Vidrine , Jeffry E. Gonion , Timothy R. Paaske , Tristan F. Schaap
IPC: G06F21/54
CPC classification number: G06F21/54
Abstract: Systems, apparatuses, methods, and computer-readable mediums for preventing return oriented programming (ROP) attacks. A compiler may insert landing pads adjacent to valid return targets in an instruction sequence. When a return instruction is executed, the processor may treat the return as suspicious if the target of the return instruction does not have an adjacent landing pad. Additionally, each landing pad may be encoded with a color, and a colored launch pad may be inserted into the instruction stream next to each return instruction. When a return instruction is executed, the processor may determine if the target of the return has a landing pad with the same color as the launch pad of the return instruction. Return-target pairs with color mismatches may be treated as suspicious and the offending process may be killed.
Abstract translation: 用于防止返回定向编程(ROP)攻击的系统,装置,方法和计算机可读介质。 编译器可以在指令序列中插入与有效返回目标相邻的着陆焊盘。 当执行返回指令时,如果返回指令的目标没有相邻的着陆垫,则处理器可以将返回值视为可疑。 此外,每个着陆垫可以用颜色编码,并且彩色的发射板可以插入每个返回指令旁边的指令流中。 当执行返回指令时,处理器可以确定返回目标是否具有与返回指令的发射台相同颜色的着陆键盘。 具有颜色不匹配的返回目标对可能被视为可疑的,并且违规进程可能被杀死。
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公开(公告)号:US20160314295A1
公开(公告)日:2016-10-27
申请号:US14696581
申请日:2015-04-27
Applicant: Apple Inc.
Inventor: Timothy R. Paaske , Weihua Mao , Shu-Yi Yu
CPC classification number: G06F21/46 , G06F21/44 , G06F21/602 , G06F21/606 , G06F21/85 , G06F2221/2137 , H04L9/088
Abstract: An apparatus, a method, and a system are presented in which the apparatus may include a security circuit, a processor, and an interface controller. The security circuit may be configured to generate a keyword. The processor may be configured to determine one or more policies to be applied to usage of the keyword, and to generate a policy value. The policy value may include one or more data bits indicative of the determined one or more policies. The interface controller may be configured to generate a message including the keyword and the policy value. The interface controller may also be configured to send the message.
Abstract translation: 提供了一种装置,方法和系统,其中装置可以包括安全电路,处理器和接口控制器。 安全电路可以被配置为生成关键字。 处理器可以被配置为确定要应用于关键字的使用的一个或多个策略,并且生成策略值。 策略值可以包括指示所确定的一个或多个策略的一个或多个数据比特。 接口控制器可以被配置为生成包括关键字和策略值的消息。 接口控制器还可以被配置为发送消息。
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公开(公告)号:US09202061B1
公开(公告)日:2015-12-01
申请号:US14696622
申请日:2015-04-27
Applicant: Apple Inc.
Inventor: R. Stephen Polzin , Fabrice L. Gautier , Mitchell D. Adler , Timothy R. Paaske , Michael J. Smith
IPC: G06F15/177 , G06F9/24 , G06F1/24 , G06F7/04 , H04N7/16 , G06F21/57 , G06F21/60 , G06F12/14 , G06F9/44 , G06F9/445 , G06F21/00
CPC classification number: G06F21/575 , G06F1/24 , G06F9/24 , G06F9/4401 , G06F9/44505 , G06F12/14 , G06F15/167 , G06F21/00 , G06F21/572 , G06F21/60 , G06F21/74 , G06F21/76 , G06F21/81
Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.
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