公开(公告)号：US20240289282A1

公开(公告)日：2024-08-29

申请号：US18173500

申请日：2023-02-23

Applicant: Apple Inc.

Inventor： Jonathan M. Redshaw ,  Winnie W. Yeung ,  Benjiman L. Goodman ,  David K. Li ,  Zelin Zhang ,  Yoong Chert Foo

IPC: G06F9/30

CPC classification number: G06F9/30079 ,  G06F9/30047 ,  G06F9/30145

Abstract: Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

公开(公告)号：US11947462B1

公开(公告)日：2024-04-02

申请号：US17653418

申请日：2022-03-03

Applicant: Apple Inc.

Inventor： Yoong Chert Foo ,  Terence M. Potter ,  Donald R. DeSota ,  Benjiman L. Goodman ,  Aroun Demeure ,  Cheng Li ,  Winnie W. Yeung

IPC: G06F12/08 ,  G06F12/0875

CPC classification number: G06F12/0875 ,  G06F2212/60

Abstract: Techniques are disclosed relating to cache footprint management. In some embodiments, execution circuitry is configured to perform operations for instructions from multiple threads in parallel. Cache circuitry may store information operated on by threads executed by the execution circuitry. Scheduling circuitry may arbitrate among threads to schedule threads for execution by the execution circuitry. Tracking circuitry may determine one or more performance metrics for the cache circuitry. Control circuitry may, based on the one or more performance metrics meeting a threshold, reduce a limit on a number of threads considered for arbitration by the scheduling circuitry, to control a footprint of information stored by the cache circuitry. Disclosed techniques may advantageously reduce or avoid cache thrashing for certain processor workloads.

公开(公告)号：US11443479B1

公开(公告)日：2022-09-13

申请号：US17324857

申请日：2021-05-19

Applicant: Apple Inc.

Inventor： Winnie W. Yeung ,  Leela Kishore Kothamasu ,  Zelin Zhang ,  Guanlan Xu ,  Eddie M. Robinson

IPC: G06F13/362 ,  G06T15/83 ,  G06T15/04 ,  G06T15/00 ,  G06F13/16

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

公开(公告)号：US20210134052A1

公开(公告)日：2021-05-06

申请号：US16673883

申请日：2019-11-04

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Karl D. Mann ,  Tyson J. Bergland ,  Winnie W. Yeung

IPC: G06T15/80 ,  G06T15/00 ,  G06T15/04 ,  G09G5/36

Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry. In some embodiments, write circuitry is configured to write the first and second compressed blocks of pixel data in a combined write to a higher level in the storage hierarchy.

公开(公告)号：US10289565B2

公开(公告)日：2019-05-14

申请号：US15610008

申请日：2017-05-31

Applicant: Apple Inc.

Inventor： Wolfgang H. Klingauf ,  Kenneth C. Dyke ,  Karthik Ramani ,  Winnie W. Yeung ,  Anthony P. DeLaurier ,  Luc R. Semeria ,  David A. Gotwalt ,  Srinivasa Rangan Sridharan ,  Muditha Kanchana

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/123 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0804

Abstract: Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.

公开(公告)号：US20250104181A1

公开(公告)日：2025-03-27

申请号：US18795437

申请日：2024-08-06

Applicant: Apple Inc.

Inventor： Karthik Ramani ,  Tyson J. Bergland ,  Leela Kishore Kothamasu ,  Hongzhou Zhao ,  Winnie W. Yeung ,  Mladen Wilder

IPC: G06T1/60 ,  G06F12/0891 ,  G06T15/00

Abstract: Techniques are disclosed relating to data compression in graphics processors. In some embodiments, cache circuitry is coupled to shader processor circuitry and is configured to store graphics data that includes a compressed block of data associated with a surface and metadata for the compressed block of data. Metadata coherence circuitry may cache the metadata for the compressed block of data, receive an indication of a write command for non-compressed data associated with the surface, wherein the write command identifies the metadata and has a different address than the compressed block of data, and determine, based on the metadata and the indication, to invalidate the compressed block of data in the cache circuitry. This may maintain read/write coherence in a cache that stores both compressed and uncompressed data, in some embodiments.

公开(公告)号：US20220375161A1

公开(公告)日：2022-11-24

申请号：US17816632

申请日：2022-08-01

Applicant: Apple Inc.

Inventor： Winnie W. Yeung ,  Leela Kishore Kothamasu ,  Zelin Zhang ,  Guanlan Xu ,  Eddie M. Robinson

IPC: G06T15/83 ,  G06F13/362 ,  G06T15/00 ,  G06T15/04 ,  G06F13/16

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

公开(公告)号：US20220374359A1

公开(公告)日：2022-11-24

申请号：US17324800

申请日：2021-05-19

Applicant: Apple Inc.

Inventor： Winnie W. Yeung ,  Cheng Li

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/02 ,  G06F13/16

Abstract: Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.

公开(公告)号：US11062507B2

公开(公告)日：2021-07-13

申请号：US16673883

申请日：2019-11-04

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Karl D. Mann ,  Tyson J. Bergland ,  Winnie W. Yeung

IPC: G06T15/80 ,  G09G5/36 ,  G06T15/04 ,  G06T15/00

Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry. In some embodiments, write circuitry is configured to write the first and second compressed blocks of pixel data in a combined write to a higher level in the storage hierarchy.

公开(公告)号：US10970223B2

公开(公告)日：2021-04-06

申请号：US16410828

申请日：2019-05-13

Applicant: Apple Inc.

Inventor： Wolfgang H. Klingauf ,  Kenneth C. Dyke ,  Karthik Ramani ,  Winnie W. Yeung ,  Anthony P. DeLaurier ,  Luc R. Semeria ,  David A. Gotwalt ,  Srinivasa Rangan Sridharan ,  Muditha Kanchana

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/123 ,  G06F12/0895 ,  G06F12/126 ,  G06F12/12

Abstract: Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.