公开(公告)号：US20240136229A1

公开(公告)日：2024-04-25

申请号：US18462242

申请日：2023-09-06

Applicant: Applied Materials, Inc.

Inventor： Jody FRONHEISER ,  Sai Hooi YEONG ,  Benjamin COLOMBEAU ,  Balasubramanian PRANATHARTHIHARAN ,  Lequn LIU

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/15 ,  H01L29/423

CPC classification number: H01L21/823412 ,  H01L21/02507 ,  H01L29/15 ,  H01L29/42392

Abstract: A method of forming a multi-layer semiconductor device on a substrate includes forming a superlattice of a plurality of alternating first layers composed of a first material and second layers formed of a second material, removing the second layers of the superlattice, etching the first material layers to form trimmed first layers therefrom, wherein the quantity of material removed from different ones of the first layers are different amounts, forming a capping layer over the first layers, measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover, and based on differences in the measurements, calculating a new thickness of the etched first layers.

公开(公告)号：US20230377997A1

公开(公告)日：2023-11-23

申请号：US18123783

申请日：2023-03-20

Applicant: Applied Materials, Inc.

Inventor： Nicolas Louis BREIL ,  Balasubramanian PRANATHARTHIHARAN ,  Benjamin COLOMBEAU ,  Anchuan WANG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/823871 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76895

Abstract: A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, and performing a selective removal process to remove the first contact layer selectively to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.

公开(公告)号：US20200161171A1

公开(公告)日：2020-05-21

申请号：US16579759

申请日：2019-09-23

Applicant: Applied Materials, Inc.

Inventor： Benjamin COLOMBEAU ,  Theresa Kramer GUARINI ,  Malcolm BEVAN ,  Rui CHENG

IPC: H01L21/762 ,  H01L21/02 ,  H01J37/32 ,  C23C16/56 ,  C23C16/24 ,  C23C16/28 ,  C23C16/50

Abstract: Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.

公开(公告)号：US20200152493A1

公开(公告)日：2020-05-14

申请号：US16579756

申请日：2019-09-23

Applicant: Applied Materials, Inc.

Inventor： Benjamin COLOMBEAU ,  Sheng-Chin KUNG ,  Patricia M. LIU

IPC: H01L21/67 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.

公开(公告)号：US20180240893A9

公开(公告)日：2018-08-23

申请号：US15792449

申请日：2017-10-24

Applicant: Applied Materials, Inc.

Inventor： Matthias BAUER ,  Hans-Joachim L. GOSSMANN ,  Benjamin COLOMBEAU

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/26 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/306 ,  H01L29/167 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/26 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02658 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/20 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.