公开(公告)号：US20200152493A1

公开(公告)日：2020-05-14

申请号：US16579756

申请日：2019-09-23

Applicant: Applied Materials, Inc.

Inventor： Benjamin COLOMBEAU ,  Sheng-Chin KUNG ,  Patricia M. LIU

IPC: H01L21/67 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.

公开(公告)号：US20170309719A1

公开(公告)日：2017-10-26

申请号：US15494981

申请日：2017-04-24

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Nam Sung KIM ,  Bingxi Sun WOOD ,  Naomi YOSHIDA ,  Sheng-Chin KUNG ,  Miao JIN

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.

公开(公告)号：US20180083104A1

公开(公告)日：2018-03-22

申请号：US15418286

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau HUANG ,  Hua CHUNG ,  Sheng-Chin KUNG ,  Xuebin LI

IPC: H01L29/167 ,  H01L29/161 ,  H01L21/225 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L29/167 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02656 ,  H01L21/02661 ,  H01L21/02667 ,  H01L21/2018 ,  H01L21/2033 ,  H01L21/2053 ,  H01L21/2252 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67184 ,  H01L21/67207 ,  H01L29/161 ,  H01L29/785

Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.

公开(公告)号：US20220173220A1

公开(公告)日：2022-06-02

申请号：US17672788

申请日：2022-02-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Nam Sung KIM ,  Bingxi Sun WOOD ,  Naomi YOSHIDA ,  Sheng-Chin KUNG ,  Miao JIN

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.

公开(公告)号：US20180166570A1

公开(公告)日：2018-06-14

申请号：US15839024

申请日：2017-12-12

Applicant: Applied Materials, Inc.

Inventor： Sheng-Chin KUNG ,  Hua CHUNG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.