公开(公告)号：US20170091097A1

公开(公告)日：2017-03-30

申请号：US15254233

申请日：2016-09-01

Applicant: ARM LIMITED

Inventor： Alex James WAUGH ,  Max John BATLEY ,  Thomas Edward ROBERTS

IPC: G06F12/0815 ,  G06F12/1027

Abstract: An apparatus comprises a translation lookaside buffer (TLB) comprising TLB entries for storing address translation data for translating virtual addresses to physical addresses. Hazard checking circuitry detects a hazard condition when two data access transactions correspond to the same physical address. The hazard checking circuitry includes a TLB entry identifier comparator to compare TLB entry identifiers identifying the TLB entries corresponding to the two data access transactions. The hazard condition is detected in dependence on whether the TLB entry identifiers match.

公开(公告)号：US20200293233A1

公开(公告)日：2020-09-17

申请号：US16353257

申请日：2019-03-14

Applicant: Arm Limited

Inventor： Alex James WAUGH ,  Geoffray Mattheiu LACOURBA ,  Andrew John TURNER ,  Sergio SCHULER

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/0837 ,  G06F9/50

Abstract: Aspects of the present disclosure relate to an interconnect comprising an interface to couple to a master device, the interface comprising buffer storage. The interface is configured to receive a request from the master device for data comprising a plurality of data blocks, the master device requiring the data blocks in a defined order. A data collator is configured to: receive the request; issue a data pull request to cause the interface to allocate buffer space in the buffer storage for buffering the requested data; and responsive to receiving a confirmation that the buffer space is allocated, provide the requested data to the buffer storage. The interface is configured to employ the buffer storage to enable re-ordering of the plurality of data blocks of the requested data, prior to outputting the plurality of data blocks to the master device; and output the plurality of data blocks to the master device in the defined order.

公开(公告)号：US20200089549A1

公开(公告)日：2020-03-19

申请号：US16135335

申请日：2018-09-19

Applicant: Arm Limited

Inventor： Fergus Wilson MACGARRY ,  Alex James WAUGH

IPC: G06F9/54 ,  G06F11/34

Abstract: A first event source generates a first indication of a first event which has occurred in the first event source, the first indication being one of a predefined set of indications corresponding to a plurality of event types. A second event source generates a second indication of a second event which has occurred in the second event source, the second indication being one of the predefined set of indications corresponding to the plurality of event types. First event selection circuitry responds to the first indication matching a selected event type of the plurality of event types to generate a first count signal and second event selection circuitry responds to the second indication matching the selected event type of the plurality of event types to generate a second count signal. Count circuitry increments a counter in response to either the first count signal or the second count signal.

公开(公告)号：US20170293567A1

公开(公告)日：2017-10-12

申请号：US15632654

申请日：2017-06-26

Applicant: ARM LIMITED

Inventor： Richard F. BRYANT ,  Kim Richard SCHUTTENBERG ,  Lilian Atieno HUTCHINS ,  Thomas Edward ROBERTS ,  Alex James WAUGH ,  Max John BATLEY

IPC: G06F12/1027 ,  G06F12/1036 ,  G06F9/30 ,  G06F12/1009 ,  G06F9/46

CPC classification number: G06F12/1027 ,  G06F9/30043 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/682

Abstract: An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. Address translation circuitry determines the physical address corresponding to the virtual address specified for a data access operation after that data access operation has progressed beyond said at least one buffer.

公开(公告)号：US20170228318A1

公开(公告)日：2017-08-10

申请号：US15392190

申请日：2016-12-28

Applicant: ARM Limited

Inventor： Davide MARANI ,  Alex James WAUGH

IPC: G06F12/0875 ,  G06F12/0864 ,  G06F12/1027

Abstract: An apparatus and method are provided for supporting multiple cache features. The apparatus provides cache storage comprising a plurality of cache ways and organised as a plurality of ways groups, where each way group comprises multiple cache ways from the plurality of cache ways. First cache feature circuitry is provided to implement a first cache feature that is applied to the way groups, and second cache feature circuitry is provided to implement a second cache feature that is applied to the way groups. Way group control circuitry is then arranged to provide a first mapping defining which cache ways belong to each way group when the first cache feature is applied to the way groups, and a second mapping defining which cache ways belong to each way group when the second cache feature is applied to the way groups. The first mapping and the second mapping are selected so as to prevent application of a cache feature to the way groups by one of the cache feature circuits from interfering with the ability of the other cache feature circuit to access at least one cache way in each of the way groups. Such an approach alleviates the risk of actions taken by one of the cache features from interfering with the ability of the other cache feature to operate as intended.

公开(公告)号：US20170076758A1

公开(公告)日：2017-03-16

申请号：US14855687

申请日：2015-09-16

Applicant: ARM Limited

Inventor： Alex James WAUGH

IPC: G11C5/14

CPC classification number: G11C5/148 ,  G06F1/3275 ,  G11C5/143 ,  G11C16/225

Abstract: There is provided an apparatus comprising power state determination circuitry to determine a power state of a processing circuit; and control circuitry to issue a control signal relating to an item of data stored in a first storage circuitry. When the power state of the processing circuit is a predetermined state, the control circuitry issues a further control signal to a second storage circuitry to indicate whether the item of data is to be retained by the second storage circuitry.

Abstract translation: 提供了一种包括功率状态确定电路以确定处理电路的功率状态的装置; 以及控制电路，以发出与存储在第一存储电路中的数据项有关的控制信号。 当处理电路的电源状态为预定状态时，控制电路向第二存储电路发出进一步的控制信号，以指示数据项是否由第二存储电路保留。

公开(公告)号：US20200327062A1

公开(公告)日：2020-10-15

申请号：US16382394

申请日：2019-04-12

Applicant: Arm Limited

Inventor： Geoffray Matthieu LACOURBA ,  Andrew John TURNER ,  Alex James WAUGH

IPC: G06F12/0868 ,  G06F13/38 ,  G06F13/14

Abstract: Circuitry comprises a data store to hold status data indicating a status of a first set of one or more devices connected to the interconnect circuitry; and control circuitry, responsive to initiation of a data handling transaction, to generate recovery data indicative of an initial state of the status data and to predict a predicted revised state of the status data applicable to resolution of the data handling transaction; the control circuitry being configured to change the status data to the predicted revised state in response to initiation of the transaction and before resolution of the transaction, and in response to a request to access the status data between the change of the status data to the predicted revised state and the resolution of the transaction, to provide access to the initial state of the status data, using the recovery data.

公开(公告)号：US20200259756A1

公开(公告)日：2020-08-13

申请号：US16269740

申请日：2019-02-07

Applicant: Arm Limited

Inventor： Geoffray Matthieu LACOURBA ,  Alex James WAUGH

IPC: H04L12/801 ,  H04L12/933

Abstract: An interconnect is provided that has a plurality of nodes, and a ring network to which each of the nodes is connected to allow packets to be transmitted between nodes. For an ordered sequence of packets one of the nodes is arranged as a source node to add each packet of the ordered sequence on to the ring network, and another of the nodes is arranged as a destination node to remove each packet of the ordered sequence from the ring network. The source node is enabled to add a packet of the ordered sequence on to the ring network without waiting for a previously added packet of the ordered sequence to be removed from the ring network by the destination node. When the destination node is unable to accept a given packet of the ordered sequence that is currently being presented to the destination node by the ring network, that given packet remains on the ring network and continues to be transmitted around the ring network such that after a respin period that given packet will be presented again to the destination node. The destination node is then arranged to prevent acceptance of at least any other packets of the ordered sequence subsequently presented to the destination node by the ring network until the destination node has accepted the given packet following at least one respin period. This can improve the efficiency of the ring network in the handling of ordered sequences of packets, whilst still ensuring the ordering constraints are met.

公开(公告)号：US20200250094A1

公开(公告)日：2020-08-06

申请号：US16266185

申请日：2019-02-04

Applicant: Arm Limited

Inventor： Alex James WAUGH ,  Geoffray Matthieu LACOURBA

IPC: G06F12/0815 ,  H04L12/747 ,  G06F12/0811 ,  G06F12/0862

Abstract: An interconnect, and method of operation of such an interconnect, are disclosed. The interconnect has a plurality of nodes, and a routing network via which information is routed between the plurality of nodes. The plurality of nodes comprises at least one slave node used to couple master devices to the interconnect, at least one master node used to couple slave devices to the interconnect, and at least one control node. Each control node is responsive to a slave node request received via the routing network from a slave node, to perform an operation to service the slave node request and, when a propagation condition is present, to issue a control node request via the routing network to a chosen master node in order to service the slave node request. The chosen master node processes the control node request in order to generate a master node response, and treats as a default destination for the master node response the control node that issued the control node request. In response to a trigger event occurring after the control node request has been issued, the control node sends an update destination request to the chosen master node that identifies a replacement destination node for the master node response. At least in the absence of an override condition, the chosen master node then sends the master node response via the routing network to the replacement destination node.

公开(公告)号：US20200174947A1

公开(公告)日：2020-06-04

申请号：US16327501

申请日：2016-10-19

Applicant: ARM LIMITED

Inventor： Alex James WAUGH ,  Dimitrios KASERIDIS ,  Klas Magnus BRUCE ,  Michael FILIPPO ,  Joseph Michael PUSDESRIS ,  Jamshed JALAL

IPC: G06F12/121 ,  G06F12/0815

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.