公开(公告)号：US20160205045A1

公开(公告)日：2016-07-14

申请号：US14596316

申请日：2015-01-14

Applicant: ARM LIMITED

Inventor： Andrew David TUNE

IPC: H04L12/935 ,  H04L12/931

CPC classification number: H04L49/30 ,  H04L49/254 ,  H04L49/503 ,  H04L49/508

Abstract: An apparatus is provided that includes switching circuitry having a plurality of source ports and a plurality of destination ports. The apparatus also includes arbitration circuitry for performing an arbitration operation on a plurality of requests presented at the plurality of source ports in order to determine, for at least one of the destination ports, one of the requests to be output from that destination port. The arbitration operation comprises applying a first arbitration policy in respect of requests presented by a first subset of the plurality of source ports, and a second arbitration policy in respect of requests presented by the plurality of source ports. The first arbitration policy is to reduce head-of-line blocking compared to the second arbitration policy. Consequently, it is possible to reduce head-of-line blocking while reducing the latency for delay intolerant requests presented at some of the source ports.

Abstract translation: 提供一种装置，其包括具有多个源端口和多个目的端口的开关电路。 该装置还包括仲裁电路，用于对在多个源端口处呈现的多个请求执行仲裁操作，以便为至少一个目的端口确定要从该目的端口输出的请求之一。 仲裁操作包括对由多个源端口的第一子集呈现的请求应用第一仲裁策略，以及针对由多个源端口呈现的请求的第二仲裁策略。 第一个仲裁政策是减少与第二个仲裁政策相比的头号封锁。 因此，可以减少线头阻塞，同时减少在一些源端口处呈现的延迟不允许请求的延迟。

公开(公告)号：US20160203093A1

公开(公告)日：2016-07-14

申请号：US14959170

申请日：2015-12-04

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Sean James SALISBURY ,  Daniel Adam SARA ,  George Robert Scott LLOYD

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F13/364 ,  G06F12/0815 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/621

Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialise transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behaviour at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behaviour. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behaviour for those write transactions.

Abstract translation: 提供了用于连接多个主设备和多个从设备的互连的互连和操作方法。 危险管理电路用于将交易序列化到重叠地址。 另外，门控电路确保在与一个或多个主设备的接口上的有序写入观察（OWO）行为，门控电路接收写入事务的写入地址传输，并且执行门控操作以将写入地址传输的门向前传播到 从设备为了确保OWO的行为。 门控电路在危害管理电路的控制下执行门控操作。 因此，对于由危险管理电路进行危险检查的写入事务，这样就不需要实施任何其他进程来专门管理这些写入事务的OWO行为。

公开(公告)号：US20160062889A1

公开(公告)日：2016-03-03

申请号：US14468536

申请日：2014-08-26

Applicant: ARM Limited

Inventor： Sean James SALISBURY ,  Andrew David TUNE ,  Jamshed JALAL ,  Mark David WERKHEISER

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F12/0831 ,  G06F2212/1016

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

公开(公告)号：US20150302193A1

公开(公告)日：2015-10-22

申请号：US14255352

申请日：2014-04-17

Applicant: ARM LIMITED

Inventor： Daniel SARA ,  Andrew David TUNE

IPC: G06F21/55 ,  G06F13/42

CPC classification number: G06F13/4221

Abstract: A system-on-chip integrated circuitry includes interconnect circuitry for connecting transaction sources with transaction destinations. A buffer circuit buffers a plurality of access transactions received from the transaction sources before they are passed on to respective transaction destinations. Hazard checking circuitry, such as identifier reuse circuitry, performs hazard checks for access transactions in parallel with snoop operations performed by snoop circuitry for managing coherence between data values stored within the plurality of cache memories. The snoop circuitry includes snoop reordering circuitry for permitting reordering of snoop responses. The snoop circuitry may issue a snoop request for a given access transaction in parallel with the hazard checking circuitry performing one or more hazard checks for that transaction.

Abstract translation: 系统级芯片集成电路包括用于将事务源与事务目的地连接的互连电路。 缓冲电路缓冲从交易源接收到的多个访问事务，然后它们被传递到相应的事务目的地。 诸如标识符重用电路之类的危险检查电路与窥探电路执行的窥探操作并行执行危险检查，用于管理存储在多个高速缓冲存储器中的数据值之间的相干性。 窥探电路包括窥探重排序电路，用于允许窥探响应的重新排序。 侦听电路可以对与该事务执行一个或多个危险检查的危险检查电路并行地发出对于给定访问事务的窥探请求。

公开(公告)号：US20230418765A1

公开(公告)日：2023-12-28

申请号：US17850072

申请日：2022-06-27

Applicant: Arm Limited

Inventor： Andrew David TUNE ,  Andrew Brookfield SWAINE

IPC: G06F12/121 ,  G06F12/0891 ,  G06F12/06

CPC classification number: G06F12/121 ,  G06F12/0891 ,  G06F12/0646

Abstract: An apparatus comprises a cache comprising a plurality of cache entries, and cache replacement control circuitry to select, in response to a cache request specifying a target address missing in the cache, a victim cache entry to be replaced with a new cache entry. The cache request specifies a partition identifier indicative of an execution environment associated with the cache request. The victim cache entry is selected based on re-reference interval prediction (RRIP) values for a candidate set of cache entries. The RRIP value for a given cache entry is indicative of a relative priority with which the given cache entry is to be selected as the victim cache entry. Configurable replacement policy configuration data is selected based on the partition identifier, and the RRIP value of the new cache entry is set to an initial value selected based on the selected configurable replacement policy configuration data.
[FIG. 1]

公开(公告)号：US20200050568A1

公开(公告)日：2020-02-13

申请号：US16659762

申请日：2019-10-22

Applicant: Arm Limited

Inventor： Guanghui GENG ,  Andrew David TUNE ,  Daniel Adam SARA ,  Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL

IPC: G06F13/364 ,  G06F12/0815 ,  G06F12/0888 ,  G06F13/40 ,  G06F13/42

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

公开(公告)号：US20190363829A1

公开(公告)日：2019-11-28

申请号：US15989226

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Andrew David TUNE ,  Guanghui GENG ,  Zheng XU

IPC: H04L1/00 ,  H04L12/707 ,  G06F13/40 ,  G06F17/50

Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

公开(公告)号：US20190266010A1

公开(公告)日：2019-08-29

申请号：US16345789

申请日：2017-12-13

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Daniel SARA ,  Guanghui GENG

IPC: G06F9/46 ,  G06F9/50 ,  G06F13/16

Abstract: A transaction handling device comprises transaction handling circuitry to handle a transaction request for a data processing transaction, the transaction request having an associated identifier such that at least an aspect of processing for each of a set of transaction requests having the same identifier must be performed in the order of issue of that set of transactions; and detection circuitry to detect the state of an indicator associated with the identifier to indicate whether that identifier relates to more than one concurrently pending transaction request.

公开(公告)号：US20190243785A1

公开(公告)日：2019-08-08

申请号：US16386321

申请日：2019-04-17

Applicant: ARM Limited

Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Alessandro GRANDE

IPC: G06F13/14

CPC classification number: G06F13/14

Abstract: Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.

公开(公告)号：US20170012901A1

公开(公告)日：2017-01-12

申请号：US15273932

申请日：2016-09-23

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Alessandro GRANDE

IPC: H04L12/937 ,  H04L12/753

CPC classification number: G06F13/14

Abstract: Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection to provide said output following completion of and in dependence upon said arbitration.

Abstract translation: 用于在多个输入之间执行仲裁并选择所述多个输入中的至少一个以提供输出的仲裁和复用电路包括：具有X个仲裁级别的树状电路的仲裁，其中X是大于1的整数; 以及具有Y复用电平的复用树电路，其中Y是大于1的整数; 其中（i）所述Y复用电平包括在第二组所述多路复用电平上游的所述复用电平的第一集合; （ii）所述第一组所述复用级别被配置为与所述X个仲裁级别中的至少一些并行操作，由此所述第一组复用级别被配置为与由所述X仲裁执行的所述仲裁并行执行部分选择 水平; 和（iii）所述第二组所述复用级别被配置为与所述X个仲裁级别串联操作，由此所述第二组复用级别完成所述选择以在完成并根据所述仲裁之后提供所述输出。