公开(公告)号：US09817661B2

公开(公告)日：2017-11-14

申请号：US14877003

申请日：2015-10-07

Applicant: ARM LIMITED

Inventor： David Raymond Lutz ,  Christopher Neal Hinds ,  Neil Burgess

IPC: G06F7/38 ,  G06F9/30 ,  G06F7/483

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/49947 ,  G06F9/30 ,  G06F9/3016

Abstract: A data processing system supports execution of program instructions having a rounding position input operand so as to generate control signals for controlling processing circuitry to process a floating point input operand with a significand value to generate an output result which depends upon a value from rounding the floating point input operand using a variable rounding point within the significand of the floating point input operand as specified by the rounding position input operand. In this way, processing operations having as inputs floating point operands and anchored number operands may be facilitated.

公开(公告)号：US09678716B2

公开(公告)日：2017-06-13

申请号：US14579435

申请日：2014-12-22

Applicant: ARM Limited

Inventor： Neil Burgess ,  David Raymond Lutz

IPC: G06F7/544 ,  G06F7/509

CPC classification number: G06F7/509 ,  G06F7/544 ,  G06F2207/5442

Abstract: An apparatus comprises processing circuitry for performing an absolute difference operation for generating an absolute difference value in response to the first operand the second operand. The processing circuitry supports variable data element sizes for data elements of the first and second operands and the absolute difference value. Each data element of the absolute difference value represents an absolute difference between corresponding data elements of the first and second operands. The processing circuitry has an adding stage for performing at least one addition to generate at least one intermediate value and an inverting stage for inverting selected bits of each intermediate value. Control circuitry generates control information based on the current data element size and status information generated in the adding stage, to identify the selected bits to be inverted in the inverting stage to convert each intermediate value into a corresponding portion of the absolute difference value.

公开(公告)号：US09665347B2

公开(公告)日：2017-05-30

申请号：US14582812

申请日：2014-12-24

Applicant: ARM Limited

Inventor： David Raymond Lutz ,  Neil Burgess ,  Christopher Neal Hinds

IPC: G06F5/00 ,  G06F7/483 ,  G06F7/499 ,  G06F9/30 ,  G06F17/16 ,  H03M7/12 ,  H03M7/24 ,  G06F11/34 ,  G06F11/36 ,  G06F5/01 ,  G06F7/38 ,  G06F7/48 ,  G06F7/507 ,  G06F9/38 ,  G06F7/506

CPC classification number: G06F7/483 ,  G06F5/012 ,  G06F7/38 ,  G06F7/48 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/49921 ,  G06F7/49942 ,  G06F7/506 ,  G06F7/507 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3885 ,  G06F11/3404 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3636 ,  G06F11/3644 ,  G06F11/3648 ,  G06F17/16 ,  G06F2201/865 ,  G06F2207/483 ,  H03M7/12 ,  H03M7/24

Abstract: An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value.

公开(公告)号：US09519456B2

公开(公告)日：2016-12-13

申请号：US14210609

申请日：2014-03-14

Applicant: ARM LIMITED

Inventor： David Raymond Lutz ,  Neil Burgess

IPC: G06F5/01 ,  G06F7/74

CPC classification number: G06F5/01 ,  G06F5/012 ,  G06F7/74

Abstract: A data processing apparatus and method are provided for performing a shift function on a binary number. The apparatus comprises count determination circuitry for determining a number of contiguous bit positions in the binary number that have a predetermined bit value, the count determination circuitry outputting a count value indicative of the number of contiguous bit positions determined. In parallel with the operation of the count determination circuitry, coarse shifting circuitry is used to determine, for at least one predetermined number of contiguous bit positions, whether that predetermined number of contiguous bit positions within the binary number has said predetermined bit value. An initial shift operation is then performed on the binary number based on that determination in order to produce an intermediate binary number. Once the count value is available from the count determination circuitry, fine shifting circuitry then performs a further shift operation on the intermediate binary number, based on the count value output by the count determination circuitry, in order to produce the result binary number. This provides an efficient mechanism for performing a shift function on a binary number, while still capturing the count value from the count determination circuitry.

Abstract translation: 提供了一种用于对二进制数执行移位功能的数据处理装置和方法。 该装置包括用于确定具有预定比特值的二进制数中的连续比特位数的计数确定电路，计数确定电路输出指示所确定的连续比特位数的计数值。 与计数确定电路的操作并行，粗移位电路用于对于至少一个预定数量的连续位位置来确定二进制数中的预定数量的连续位位置是否具有所述预定位值。 然后基于该确定对二进制数执行初始移位操作，以便产生中间二进制数。 一旦从计数确定电路获得计数值，微移位电路然后基于计数确定电路输出的计数值对中间二进制数执行进一步的移位操作，以便产生结果二进制数。 这提供了一种用于在二进制数字上执行移位功能的有效机制，同时仍然从计数确定电路捕获计数值。

公开(公告)号：US20160092168A1

公开(公告)日：2016-03-31

申请号：US14498118

申请日：2014-09-26

Applicant: ARM Limited

Inventor： David Raymond Lutz ,  Neil Burgess

IPC: G06F7/485 ,  G06F5/00

CPC classification number: H03M7/24

Abstract: A data processing apparatus has floating-point add circuitry to perform a floating-point addition operation for adding or subtracting two floating-point values. The apparatus also has conversion circuitry to perform a conversion operation to convert a first floating-point value into a second value having a different format. The conversion circuitry is capable of converting to an integer or fixed-point value. The conversion circuitry is physically distinct from the floating-point add circuitry.

Abstract translation: 数据处理装置具有浮点加法电路，用于执行用于相加或减去两个浮点值的浮点加法运算。 该装置还具有转换电路，用于执行转换操作以将第一浮点值转换为具有不同格式的第二值。 转换电路能够转换为整数或定点值。 转换电路在物理上不同于浮点加法电路。

公开(公告)号：US09262123B2

公开(公告)日：2016-02-16

申请号：US13955324

申请日：2013-07-31

Applicant: ARM LIMITED

Inventor： Neil Burgess ,  David Raymond Lutz

IPC: G06F7/50 ,  G06F7/499 ,  G06F7/506

CPC classification number: G06F7/49947 ,  G06F7/50 ,  G06F7/506

Abstract: A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N

Abstract translation: 一种处理装置支持缩小和舍入的算术运算，其响应于每个包括至少一个W位数据元素的两个操作数产生包括至少一个X位结果数据元素的结果值，每个X位 结果数据元素表示舍入到X位值（W> X）的两个操作数的相应W位数据元素的和或差。 使用多个N位加法（N

公开(公告)号：US20240036824A1

公开(公告)日：2024-02-01

申请号：US18213469

申请日：2023-06-23

Applicant: Arm Limited

Inventor： Neil Burgess ,  Sangwon Ha ,  Partha Prasun Maji

IPC: G06F7/499

CPC classification number: G06F7/49947 ,  G06F7/49915

Abstract: In a data processor, an input value having a sign, an exponent and a significand is encoded by determining an exponent difference between a base exponent and the exponent. When the exponent difference is not less than a first threshold, only the exponent difference, or a designated value, is encoded to a payload of the output value and one or more tag bits of the output value are set to a first value. When the exponent difference is less than the first threshold, the significand and exponent difference are encoded to the payload of an output value and, optionally, the one or more tag bits of the output value. A sign bit in the output value is set corresponding to the sign of the input value, and the output value is stored.

公开(公告)号：US20240036822A1

公开(公告)日：2024-02-01

申请号：US17878291

申请日：2022-08-01

Applicant: Arm Limited

Inventor： Neil Burgess ,  Sangwon Ha ,  Partha Prasun Maji

IPC: G06F7/487 ,  G06F9/30

CPC classification number: G06F7/4876 ,  G06F9/3016

Abstract: A data processing apparatus is configured to determine a product of two operands stored in an Extended Block Floating-Point format. The operands are decoded, based on their tags and payloads, to generate exponent differences and at least the fractional parts of significands. The significands are multiplied to generate an output significand and shared exponents and exponent differences of the operands are combined to generate an output exponent. Signs of the operands may also be combined to provide an output sign. The apparatus may be combined with an accumulator having one or more lanes to provide an apparatus for determining dot products.

公开(公告)号：US11106465B2

公开(公告)日：2021-08-31

申请号：US16650999

申请日：2018-11-15

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Nigel John Stephens ,  Neil Burgess ,  Grigorios Magklis

IPC: G06F9/30 ,  G06F7/50

Abstract: Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.

公开(公告)号：US11055096B2

公开(公告)日：2021-07-06

申请号：US15862728

申请日：2018-01-05

Applicant: Arm Limited

Inventor： Neil Burgess ,  Lee Evan Eisen

IPC: G06F9/34 ,  G06F9/38 ,  G06F12/02 ,  G06F9/30

Abstract: An in-order processor has a mapping storage element to store current register mapping information identifying, for each of two or more architectural register specifiers, which physical register specifies valid data for that architectural register specifier. At least one checkpoint storage element stores checkpoint register mapping corresponding to a checkpoint of previous architectural state. This enables checkpoints to be saved and restored simply by transferring mapping information between the mapping and checkpoint storage elements, rather than transferring the actual state data.