公开(公告)号：US07619294B1

公开(公告)日：2009-11-17

申请号：US11262173

申请日：2005-10-28

申请人： Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

发明人： Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

摘要翻译： 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 首先，在集成电路基板中蚀刻沟槽。 然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。 然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容 要减少

公开(公告)号：US06656805B2

公开(公告)日：2003-12-02

申请号：US10304631

申请日：2002-11-26

申请人： Arvind Kamath ,  Rajiv Patel ,  Ravindra M. Kapre

发明人： Arvind Kamath ,  Rajiv Patel ,  Ravindra M. Kapre

IPC分类号： H01L21336

CPC分类号： H01L21/823462

摘要： A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.

公开(公告)号：US06586291B1

公开(公告)日：2003-07-01

申请号：US10214618

申请日：2002-08-08

申请人： Arvind Kamath ,  Ruggero Castagnetti

发明人： Arvind Kamath ,  Ruggero Castagnetti

IPC分类号： H01L218238

CPC分类号： H01L27/1087 ,  H01L27/10894 ,  H01L29/66181

摘要： A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.

摘要翻译： 具有在硅衬底中形成的晶体管和电容器的存储单元。 电容器形成有在硅衬底的投影表面区域中蚀刻的下导电板。 下导电板具有至少一个vee形状的横截面，其中，vee的侧面与硅衬底的顶表面成约五十五度的角度。 下导电板的表面积比其中蚀刻下导电板的硅衬底的投影表面积大约百分之七十三。 电容器介电层由邻近下导电板设置的第一沉积介电层形成。 顶部导电板设置在电容器电介质层附近并与下部导电板相对。 晶体管形成为具有由沟道区域分离的源极和漏极区域以及由第一沉积介电层形成的栅极电介质层。

公开(公告)号：US06562729B2

公开(公告)日：2003-05-13

申请号：US10171700

申请日：2002-06-14

申请人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

发明人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

IPC分类号： H01L2131

CPC分类号： H01L21/823462

摘要： Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

公开(公告)号：US06436845B1

公开(公告)日：2002-08-20

申请号：US09723516

申请日：2000-11-28

申请人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

发明人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

IPC分类号： H01L2131

CPC分类号： H01L21/823462

摘要： Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

公开(公告)号：US08296943B2

公开(公告)日：2012-10-30

申请号：US12467121

申请日：2009-05-15

申请人： Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

发明人： Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： G08B13/242 ,  B31D1/025 ,  G06K19/07783 ,  G06K19/07798 ,  G08B13/2414 ,  G08B13/2431 ,  G08B13/2437 ,  G08B13/2442 ,  H01G4/18 ,  Y10T29/413 ,  Y10T29/435 ,  Y10T29/49016 ,  Y10T29/49128 ,  Y10T29/49155

摘要： The present invention relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.

摘要翻译： 本发明涉及具有并联或串联连接的电容器的监视和/或识别装置以及制造和使用这些装置的方法。 具有并联连接电容器的器件，其中一个电容器用相对较厚的电容器电介质制造，另一个电容器由相对薄的电容器电介质制成，实现了高精度电容和低击穿电压，以便相对容易的监视标签去激活。 具有串联连接的电容器的装置增加了小电容器的横向尺寸。 这使得使用可能具有相对有限的分辨能力的技术来制造电容器更容易。

公开(公告)号：US08264359B2

公开(公告)日：2012-09-11

申请号：US12249754

申请日：2008-10-10

申请人： Vivek Subramanian ,  Patrick Smith ,  Vikram Pavate ,  Arvind Kamath ,  Criswell Choi ,  Aditi Chandra ,  James Montague Cleeves

发明人： Vivek Subramanian ,  Patrick Smith ,  Vikram Pavate ,  Arvind Kamath ,  Criswell Choi ,  Aditi Chandra ,  James Montague Cleeves

IPC分类号： G08B13/14 ,  G06K19/06

CPC分类号： G08B13/2431 ,  G06K19/067 ,  G06K19/07749 ,  G08B13/242 ,  G08B13/2437

摘要： The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.

摘要翻译： 本发明涉及制造用于监视/识别标签或装置的电容器的方法，以及使用这种监视/识别装置的方法。 根据本发明的方法制造并用于本文所述的监视/识别装置中的电容器包括印刷的导电和电介质层。 本发明的方法和装置改进了与常规金属 - 塑料 - 金属电容器相关的制造公差以及在监视/识别标签或装置中使用的电容器的失活可靠性。

公开(公告)号：US07709307B2

公开(公告)日：2010-05-04

申请号：US11842884

申请日：2007-08-21

申请人： Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

发明人： Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L21/28518 ,  H01L21/288 ,  H01L21/76801 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/7881

摘要： A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.

摘要翻译： 公开了一种非易失性存储单元，其具有位于相同水平位置并且间隔开预定距离的第一和第二半岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。 在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

公开(公告)号：US07701011B2

公开(公告)日：2010-04-20

申请号：US11888942

申请日：2007-08-03

申请人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

发明人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/12 ,  H01L27/1292 ,  H01L29/78618

摘要： An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film on the second semiconductor islands, and a metal layer in electrical contact with the first and second semiconductor islands. The first semiconductor islands and the first dielectric film contain a first diffusible dopant, and the second semiconductor islands and the second dielectric layer film contain a second diffusible dopant different from the first diffusible dopant. The present electronic device can be manufactured using printing technologies, thereby enabling high-throughput, low-cost manufacturing of electrical circuits on a wide variety of substrates.

摘要翻译： 一种电子器件，包括衬底，衬底上的多个第一半导体岛，衬底上的多个第二半导体岛，半导体岛的第一子集上的第一电介质膜，第二半导体岛上的第二电介质膜， 以及与第一和第二半导体岛电接触的金属层。 第一半导体岛和第一介电膜包含第一可扩散掺杂剂，第二半导体岛和第二介电层膜含有不同于第一可扩散掺杂剂的第二可扩散掺杂物。 本电子装置可以使用印刷技术制造，从而能够在各种基板上实现高通量，低成本的电路制造。

公开(公告)号：US20090065776A1

公开(公告)日：2009-03-12

申请号：US12114741

申请日：2008-05-02

申请人： Erik SCHER ,  Steven Molesa ,  Joerg Rockenberger ,  Arvind Kamath ,  Ikuo Mori

发明人： Erik SCHER ,  Steven Molesa ,  Joerg Rockenberger ,  Arvind Kamath ,  Ikuo Mori

IPC分类号： H01L29/04 ,  C08L83/00 ,  H01L29/06 ,  H01L29/16 ,  H01L21/208

CPC分类号： C09D5/24 ,  C09D11/101 ,  C09D11/322 ,  C09D11/36 ,  C09D11/54 ,  H01B3/02 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28008 ,  H01L27/1292 ,  H01L29/6675 ,  H01L29/78696 ,  Y10T428/24802

摘要： Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.

摘要翻译： 实施例涉及从含有材​​料前体的油墨印刷特征。 在一些实施例中，材料包括电活性材料，例如半导体，金属或其组合。 在另一个实施例中，该材料包括电介质。 这些实施例提供改进的印刷工艺条件，其允许更精确地控制印刷线或其它特征的形状，轮廓和尺寸。 组合物和/或方法通过增加油墨中组分的粘度和质量负载来改善对钉扎的控制。 因此，示例性方法包括在基板上以图案印刷包含材料前体和溶剂的油墨; 以图案沉淀前体以形成钉扎线; 基本上蒸发溶剂以形成由钉扎线限定的材料前体的特征; 并将材料前体转化成图案化材料。