利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

60 条记录 (耗时 0.034 秒)

    METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT
    2.
    发明授权
    METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT 有权
    在混合集成电路的某些晶体管中减少硅氧烷栅绝缘体厚度的方法，以获得具有混合电路的其他晶体管的栅绝缘体厚度增加的差异

    公开(公告)号：US06521549B1

    公开(公告)日：2003-02-18

    申请号：US09724225

    申请日：2000-11-28

    申请人： Arvind Kamath ,  Rajiv Patel ,  Ravindra M. Kapre

    发明人： Arvind Kamath ,  Rajiv Patel ,  Ravindra M. Kapre

    IPC分类号： H01L21469

    CPC分类号： H01L21/823462

    摘要： A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.

    摘要翻译： 数字开关晶体管的相对薄的栅极绝缘体由氮氧化硅层形成，其最初通过在硅衬底中注入氮原子并氧化氮和硅而形成。 已经发现，作为氧氮化硅层的一部分形成二氧化硅的外层。 从氮氧化硅层中除去二氧化硅外层留下基本上只有氮氧化硅的薄剩余层作为栅极绝缘体。 例如，大约15-21埃的较薄的栅极绝缘体可以由例如60埃的生长厚度形成。 用于数字和模拟晶体管的栅极绝缘体可以同时形成，通过使用常规氮注入技术，可以获得更大的厚度差。

    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit
    3.
    发明授权
    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit 有权

    公开(公告)号：US06562729B2

    公开(公告)日：2003-05-13

    申请号：US10171700

    申请日：2002-06-14

    申请人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    发明人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    IPC分类号： H01L2131

    CPC分类号： H01L21/823462

    摘要： Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit
    4.
    发明授权
    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit 有权

    公开(公告)号：US06436845B1

    公开(公告)日：2002-08-20

    申请号：US09723516

    申请日：2000-11-28

    申请人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    发明人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    IPC分类号： H01L2131

    CPC分类号： H01L21/823462

    摘要： Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

    Etch resistant shallow trench isolation in a semiconductor wafer
    5.
    发明授权
    Etch resistant shallow trench isolation in a semiconductor wafer 失效
    在半导体晶片中进行耐腐蚀浅沟槽隔离

    公开(公告)号：US06586814B1

    公开(公告)日：2003-07-01

    申请号：US09735084

    申请日：2000-12-11

    申请人： Rajiv Patel ,  David Chan ,  Arvind Kamath ,  Ken Rafftesaeth ,  Venkatesh P. Gopinath

    发明人： Rajiv Patel ,  David Chan ,  Arvind Kamath ,  Ken Rafftesaeth ,  Venkatesh P. Gopinath

    IPC分类号： H01L2900

    CPC分类号： H01L21/76224

    摘要： A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed of an insulating material, such as an oxide, in a recess formed into the wafer. An etch resistant material, such as BTBAS nitride, is placed over the insulating material in the recess. The etch resistant material protects the insulating material from erosion due to subsequent semiconductor fabrication process steps, so the integrity of the isolating trench and the planarity of the wafer are generally maintained.

    摘要翻译： 在活性组分区域之间的半导体晶片中形成浅隔离沟槽，以将活性组分彼此电隔离。 隔离沟槽主要由形成在晶片中的凹部中的绝缘材料（例如氧化物）形成。 诸如BTBAS氮化物的耐蚀刻材料放置在凹槽中的绝缘材料上。 耐蚀刻材料保护绝缘材料免受由于随后的半导体制造工艺步骤的侵蚀，因此通常保持隔离沟槽的完整性和晶片的平面性。

    Printed non-volatile memory
    6.
    发明授权
    Printed non-volatile memory 有权
    打印的非易失性存储器

    公开(公告)号：US08796774B2

    公开(公告)日：2014-08-05

    申请号：US13585673

    申请日：2012-08-14

    申请人： Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

    发明人： Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

    IPC分类号： H01L29/66 ,  H01L29/788

    CPC分类号： H01L21/28518 ,  H01L21/288 ,  H01L21/76801 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/7881

    摘要： A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.

    摘要翻译： 公开了一种非易失性存储单元，其具有位于相同水平位置并且间隔开预定距离的第一和第二半岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。 在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

    Printed Dopant Layers
    7.
    发明申请
    Printed Dopant Layers 有权
    印刷掺杂层

    公开(公告)号：US20140094004A1

    公开(公告)日：2014-04-03

    申请号：US13633816

    申请日：2012-10-02

    申请人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    发明人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1292 ,  H01L29/66757

    摘要： A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

    摘要翻译： 一种用于制造诸如MOS晶体管的电子器件的方法，包括以下步骤：在电功能衬底上形成多个半导体岛，在第一半导体岛子集上或第二子体上印刷第一介电层， 在半导体岛的第二子集上或之上，以及退火。 第一介电层包含第一掺杂剂，并且（任选的）第二介电层包含不同于第一掺杂剂的第二掺杂剂。 电介质层，半导体岛和衬底被充分退火以将第一掺杂剂扩散到半导体岛的第一子集中，并且当存在时将第二掺杂剂扩散到半导体岛的第二子集中。

    Profile engineered, electrically active thin film devices
    8.
    发明授权
    Profile engineered, electrically active thin film devices 有权
    型材设计，电活性薄膜器件

    公开(公告)号：US08426905B2

    公开(公告)日：2013-04-23

    申请号：US12243880

    申请日：2008-10-01

    申请人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    发明人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    IPC分类号： H01L29/788

    CPC分类号： H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

    摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

    摘要翻译： 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。