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11.发明授权公开(公告)号：US08669794B2
公开(公告)日：2014-03-11
申请号：US13401296
申请日：2012-02-21
IPC分类号： H03L7/06
CPC分类号： G01R19/255 , G04F10/005
摘要： A circuit for detecting a voltage change is described. The circuit includes a supply insensitive pulse generator that generates a pulse signal. The circuit also includes a time-to-digital converter coupled to the supply insensitive pulse generator. The time-to-digital converter generates a digital signal based on the pulse signal and a voltage. The circuit also includes a controller coupled to the time-to-digital converter that detects a voltage change based on the digital signal.
摘要翻译： 描述用于检测电压变化的电路。 电路包括产生脉冲信号的电源不敏感脉冲发生器。 电路还包括耦合到不敏感脉冲发生器的时间 - 数字转换器。 时间 - 数字转换器基于脉冲信号和电压产生数字信号。 电路还包括耦合到时间 - 数字转换器的控制器，其基于数字信号来检测电压变化。
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公开(公告)号：US07880554B2
公开(公告)日：2011-02-01
申请号：US12432515
申请日：2009-04-29
摘要： A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted. In a further exemplary embodiment, a clock detector control signal is configured to control the multiplexer to select the low-jitter oscillator output signal as the clock signal input to the power supply when the low-jitter oscillator output frequency is stable.
摘要翻译： 描述了包括具有用于噪声敏感模拟电路的自适应开关频率电路的电压调节器的装置，例如具有锁相环（PLL）和压控振荡器（VCO）的振荡系统。 在示例性实施例中，该器件包括参考时钟振荡器，低抖动振荡器，包括用于调节低抖动振荡器的电源电压的时钟信号输入的电源;产生时钟检测器控制信号的时钟检测器 当低抖动振荡器输出频率稳定时，以及多路复用器在参考时钟振荡器输出信号和低抖动振荡器输出信号之间选择时钟信号输入到电源，以减轻低电平时钟周期抖动的影响， 当时钟检测器控制信号被置位时，抖动振荡器输出信号。 在另一示例性实施例中，时钟检测器控制信号被配置为当低抖动振荡器输出频率稳定时，控制多路复用器选择低抖动振荡器输出信号作为输入到电源的时钟信号。
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公开(公告)号：US07724092B2
公开(公告)日：2010-05-25
申请号：US11866851
申请日：2007-10-03
申请人： Xiaohong Quan , Marzio Pedrali-Noy
发明人： Xiaohong Quan , Marzio Pedrali-Noy
IPC分类号： H03F3/68
摘要： A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor.
摘要翻译： 描述了具有慢高增益路径和快速低增益路径的双路电流放大器。 在一种设计中，慢的高增益路径是用正反馈回路实现的，并且具有大于1的增益和由极确定的带宽。 快速低增益路径具有单位增益和宽带宽。 两个信号路径接收输入电流并提供第一和第二电流。 夏季对第一和第二电流求和，并为双路电流放大器提供输出电流。 双路电流放大器可以用第一和第二电流镜来实现。 第一电流镜可以实现快速低增益路径。 第一和第二电流镜可以耦合在一起并实现慢速高增益路径。 第一电流镜可以用P-FET实现。 第二电流镜可以用N-FET，运算放大器和电容器来实现。
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公开(公告)号：US07148460B2
公开(公告)日：2006-12-12
申请号：US10809931
申请日：2004-03-25
IPC分类号： H01J40/14
CPC分类号： H04N5/335 , H04N5/32 , H04N5/3692
摘要： An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.
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公开(公告)号：US07940100B2
公开(公告)日：2011-05-10
申请号：US11860472
申请日：2007-09-24
申请人： Mustafa Keskin , Marzio Pedrali-Noy
发明人： Mustafa Keskin , Marzio Pedrali-Noy
IPC分类号： H03L7/06
CPC分类号： H03K3/037
摘要： Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to a data output. The synchronous circuit receives input data and provides output data with a propagation delay. The delay circuit receives an input signal and provides a delayed input signal having a delay matching the propagation delay of the synchronous circuit. The delay circuit includes at least two logic gates in the forward path of the synchronous circuit. The synchronous and delay circuits may be implemented based on the same or similar circuit architecture. The delay circuit may be based on a replica of the synchronous circuit, with the replica having feedback loops broken and clock input coupled to appropriate logic value to always enable the delay circuit.
摘要翻译： 描述了能够提供与同步电路的传播延迟紧密匹配的延迟的延迟电路。 在一种设计中，一种装置包括同步电路和延迟电路。 同步电路包括从数据输入到数据输出的正向路径。 同步电路接收输入数据并提供具有传播延迟的输出数据。 延迟电路接收输入信号并提供具有与同步电路的传播延迟匹配的延迟的延迟输入信号。 延迟电路在同步电路的正向路径中包括至少两个逻辑门。 同步和延迟电路可以基于相同或相似的电路架构来实现。 延迟电路可以基于同步电路的副本，其中复制品具有反馈回路断开，并且时钟输入耦合到适当的逻辑值以总是使能延迟电路。
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公开(公告)号：US20090091393A1
公开(公告)日：2009-04-09
申请号：US11866851
申请日：2007-10-03
申请人： Xiaohong Quan , Marzio Pedrali-Noy
发明人： Xiaohong Quan , Marzio Pedrali-Noy
IPC分类号： H03F3/04
摘要： A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor.
摘要翻译： 描述了具有慢高增益路径和快速低增益路径的双路电流放大器。 在一种设计中，慢的高增益路径是用正反馈回路实现的，并且具有大于1的增益和由极确定的带宽。 快速低增益路径具有单位增益和宽带宽。 两个信号路径接收输入电流并提供第一和第二电流。 夏季对第一和第二电流求和，并为双路电流放大器提供输出电流。 双路电流放大器可以用第一和第二电流镜来实现。 第一电流镜可以实现快速低增益路径。 第一和第二电流镜可以耦合在一起并实现慢速高增益路径。 第一电流镜可以用P-FET实现。 第二电流镜可以用N-FET，运算放大器和电容器来实现。
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公开(公告)号：US20090079483A1
公开(公告)日：2009-03-26
申请号：US11860472
申请日：2007-09-24
申请人： Mustafa Keskin , Marzio Pedrali-Noy
发明人： Mustafa Keskin , Marzio Pedrali-Noy
CPC分类号： H03K3/037
摘要： Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to a data output. The synchronous circuit receives input data and provides output data with a propagation delay. The delay circuit receives an input signal and provides a delayed input signal having a delay matching the propagation delay of the synchronous circuit. The delay circuit includes at least two logic gates in the forward path of the synchronous circuit. The synchronous and delay circuits may be implemented based on the same or similar circuit architecture. The delay circuit may be based on a replica of the synchronous circuit, with the replica having feedback loops broken and clock input coupled to appropriate logic value to always enable the delay circuit.
摘要翻译： 描述了能够提供与同步电路的传播延迟紧密匹配的延迟的延迟电路。 在一种设计中，一种装置包括同步电路和延迟电路。 同步电路包括从数据输入到数据输出的正向路径。 同步电路接收输入数据并提供具有传播延迟的输出数据。 延迟电路接收输入信号并提供具有与同步电路的传播延迟匹配的延迟的延迟输入信号。 延迟电路在同步电路的正向路径中包括至少两个逻辑门。 同步和延迟电路可以基于相同或相似的电路架构来实现。 延迟电路可以基于同步电路的副本，其中复制品具有反馈回路断开，并且时钟输入耦合到适当的逻辑值以总是使能延迟电路。
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18.发明授权公开(公告)号：US08159888B2
公开(公告)日：2012-04-17
申请号：US12714767
申请日：2010-03-01
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an edge of a reference signal. The memory circuit can be included in a memory interface. Furthermore, in some embodiments, a strobe signal can be used as the reference signal.
摘要翻译： 存储电路包括延迟模块，其接收选通信号并产生延迟的选通信号。 存储器电路还包括校准模块，当校准模块识别延迟的选通信号在参考信号的边缘的预定接近度内时，启动对延迟模块的重新校准。 存储器电路可以包括在存储器接口中。 此外，在一些实施例中，可以使用选通信号作为参考信号。
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19.发明申请公开(公告)号：US20130214831A1
公开(公告)日：2013-08-22
申请号：US13401296
申请日：2012-02-21
CPC分类号： G01R19/255 , G04F10/005
摘要： A circuit for detecting a voltage change is described. The circuit includes a supply insensitive pulse generator that generates a pulse signal. The circuit also includes a time-to-digital converter coupled to the supply insensitive pulse generator. The time-to-digital converter generates a digital signal based on the pulse signal and a voltage. The circuit also includes a controller coupled to the time-to-digital converter that detects a voltage change based on the digital signal.
摘要翻译： 描述用于检测电压变化的电路。 电路包括产生脉冲信号的电源不敏感脉冲发生器。 电路还包括耦合到不敏感脉冲发生器的时间 - 数字转换器。 时间 - 数字转换器基于脉冲信号和电压产生数字信号。 电路还包括耦合到时间 - 数字转换器的控制器，其基于数字信号来检测电压变化。
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20.发明授权Techniques for minimizing control voltage noise due to charge pump leakage in phase locked loop circuits 失效在锁相环电路中由于电荷泵漏电而使控制电压噪声最小化的技术公开(公告)号：US08164369B2
公开(公告)日：2012-04-24
申请号：US12367980
申请日：2009-02-09
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/18
摘要： Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump output noise in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval. A sampling switch controller is configured to adaptively control the width of the sampling interval in order to mitigate the effects of output noise from the charge pump by closing the sampling switch in advance of the phase comparison operation and opening the sampling switch when the phase comparison operation is completed.
摘要翻译： 提供了用于自适应地控制环路滤波器采样间隔以减轻包括锁相环电路的装置中的电荷泵输出噪声的影响的技术。 一方面，该装置包括压控振荡器（VCO），提供相位比较操作的相位频率检测器（PFD），提供控制电压以将VCO锁定到所需工作频率的环路滤波器，以及配置 以响应于UP脉冲和DOWN脉冲中的至少一个向环路滤波器提供输出信号。 该装置还包括一个采样开关，耦合在环路滤波器的输入端，电荷泵的输出端之间，并以采样间隔为特征。 采样开关控制器被配置为自适应地控制采样间隔的宽度，以便在相位比较操作之前关闭采样开关并在相位比较操作时打开采样开关来减轻来自电荷泵的输出噪声的影响 完成了。
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