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11.发明授权Integrated circuit bus architecture including a full-swing, clocked, common-gate receiver for fast on-chip signal transmission 有权集成电路总线架构，包括全频，时钟，共门接收器，用于快速片上信号传输公开(公告)号：US06353342B1
公开(公告)日：2002-03-05
申请号：US09702121
申请日：2000-10-30
IPC分类号： G11C706
CPC分类号： H04L25/0292 , H04L25/0278 , H04L25/028
摘要： An integrated circuit (IC) bus architecture is disclosed. The bus architecture includes a receiver for fast on-chip signal transmission. The receiver includes a first gate device having one terminal connected to a voltage source and a gate terminal connectable to receive a sense signal. A second gate device includes one terminal connected to another terminal of the first gate device, a gate terminal connectable to receive the sense signal and another terminal serving as an input terminal of the receiver and connectable to an interconnect bus to receive input signals from other components on the IC chip. The receiver also includes a third gate device having one terminal connected to a voltage source and another terminal serving as an output terminal of the receiver and connected to the other terminal of the first gate device. The receiver further includes an inverter having an input terminal connected to the output of the receiver and having an output terminal connected to a gate terminal of the third gate device. The input of the receiver is capable of being pre-discharged to a low signal and the output of the receiver is capable of being pre-charged to a high signal for substantially instantaneous transmission of input signals received by the receiver.
摘要翻译： 公开了一种集成电路（IC）总线架构。 总线架构包括用于快速片上信号传输的接收器。 接收机包括具有连接到电压源的一个端子和可连接以接收感测信号的栅极端子的第一栅极器件。 第二栅极器件包括连接到第一栅极器件的另一个端子的一个端子，可连接的感测信号的栅极端子和用作接收器的输入端子的另一个端子，并且可连接到互连总线以从其它部件接收输入信号 在IC芯片上。 接收机还包括具有连接到电压源的一个端子和用作接收器的输出端的另一个端子并连接到第一门装置的另一端的第三门装置。 接收机还包括一个反相器，其具有连接到接收器的输出的输入端，并且具有连接到第三门装置的栅极端的输出端。 接收机的输入能够被预放电到低信号，并且接收机的输出能够被预充电到高信号，以便接收器接收的输入信号的基本瞬时传输。
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12.发明授权公开(公告)号：US06351150B1
公开(公告)日：2002-02-26
申请号：US09658793
申请日：2000-09-11
IPC分类号： H03K19096
CPC分类号： H03K19/0016 , H03K19/01855
摘要： A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.
摘要翻译： 利用动态驱动技术的高性能互连能够在低数据交换活动期间降低功耗。 提供了电路，其将动态驱动器电路中的评估操作的性能限制为时钟周期，在该周期期间，互连的当前输入位与先前的输入位不同。 因此，在低数据切换活动的时段期间，谨慎地执行驱动器输出的评估操作和随后的预充电。 还提供了一个输出电路，用于解码在其接收端处流经互连的数据流。 使用本发明的原理，可以通过使用静态CMOS技术的互连的交换活动来实现动态驱动器的性能优点。
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公开(公告)号：US06838910B2
公开(公告)日：2005-01-04
申请号：US10633127
申请日：2003-08-01
IPC分类号： H03K3/356 , H03K19/096
CPC分类号： H03K3/356113 , H03K3/356173
摘要： A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.
摘要翻译： 公开了一种具有自动切断机构的双轨静态逻辑门。 在一个实施例中，第一轨道的输出耦合到第二轨道的上拉装置的输入端，反之亦然。 交叉耦合允许静态门的自我截止机制正常工作，并提供具有比常规静态门更低的电容的组件。 较低的电容导致更快的静态栅极。
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公开(公告)号：US06791364B2
公开(公告)日：2004-09-14
申请号：US09896252
申请日：2001-06-28
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , G01R31/2855
摘要： A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.
摘要翻译： 具有用于老化的条件保持器的动态电路。 在所描述的实施例中，提供了仅在老化测试期间有效的条件保持器，其中条件保持器的尺寸大于标准保持器，以便补偿动态电路中的附加泄漏电流。
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![Flash [II]-Domino: a fast dual-rail dynamic logic style](/abs-image/US/2004/04/06/US06717441B2/abs.jpg.150x150.jpg)
公开(公告)号：US06717441B2
公开(公告)日：2004-04-06
申请号：US10021544
申请日：2001-10-22
IPC分类号： H03K19096
CPC分类号： H03K3/356113 , H03K3/356173
摘要： A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.
摘要翻译： 公开了一种具有自动切断机构的双轨静态逻辑门。 在一个实施例中，第一轨道的输出耦合到第二轨道的上拉装置的输入端，反之亦然。 交叉耦合允许静态门的自我截止机制正常工作，并提供具有比常规静态门更低的电容的组件。 较低的电容导致更快的静态栅极。
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公开(公告)号：US06519178B2
公开(公告)日：2003-02-11
申请号：US10172107
申请日：2002-06-13
IPC分类号： G11C1140
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.
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公开(公告)号：US08577948B2
公开(公告)日：2013-11-05
申请号：US12886012
申请日：2010-09-20
申请人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
发明人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
IPC分类号： G06F7/483
CPC分类号： G06F9/3893 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036
摘要： In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，如果第一和第二操作数的至少一部分与第三操作数之间的差小于阈值，则处理器包括具有第一路径以处理指令的执行的乘法累加（MAC）单元，以及 如果差值大于阈值，则处理指令执行的第二路径。 基于该差异，第三操作数的至少一部分将被提供给MAC单元的乘法器或第二路径的压缩器。 描述和要求保护其他实施例。
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公开(公告)号：US07913101B2
公开(公告)日：2011-03-22
申请号：US11824410
申请日：2007-06-29
申请人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
发明人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
IPC分类号： G06F1/12
CPC分类号： H03K5/135 , H03K2005/00058 , H03K2005/00234 , H03K2005/00241
摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.
摘要翻译： 一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。 时钟相位的第一个数量与第二个时钟相位数不同。 所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。
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公开(公告)号：US07840885B2
公开(公告)日：2010-11-23
申请号：US11860493
申请日：2007-09-24
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译： 移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。
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20.发明授权公开(公告)号：US07606062B2
公开(公告)日：2009-10-20
申请号：US12006238
申请日：2007-12-31
IPC分类号： G11C11/40
CPC分类号： G11C11/419
摘要： Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.
摘要翻译： 描述了关于超低电压存储器位单元的方法和装置。 在一个实施例中，使用对由互补写入字线控制的数据存储节点的冗余路径提供超低电压存储器件。 还描述了其它实施例。
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