公开(公告)号：US07650453B2

公开(公告)日：2010-01-19

申请号：US11663036

申请日：2005-09-02

申请人： Sunao Torii

发明人： Sunao Torii

IPC分类号： G06F13/00

CPC分类号： G06F13/362 ,  G06F13/1631

摘要： A technique for improving usage efficiency of a shared resource and improving processing capacity in an information processing apparatus, without increasing the transmission rate or the bit width of a bus is disclosed. Multiple bus interfaces are connected to at least one shared resource. The multiple bus interfaces are connected to a multi-layer bus respectively. Furthermore, data buffers for holding read data and write data respectively are provided for each bus interface. An arbiter arbitrates access requests from the respective bus interfaces, and the shared resource reads and writes data in response to the access request which has been given an access right.

摘要翻译： 公开了一种用于提高共享资源的使用效率并提高信息处理设备中的处理能力的技术，而不增加总线的传输速率或位宽。 多个总线接口连接到至少一个共享资源。 多总线接口分别连接到多层总线。 此外，为每个总线接口提供用于保持读取数据和写入数据的数据缓冲器。 仲裁者对来自相应总线接口的访问请求进行仲裁，并且共享资源响应已被授予访问权限的访问请求读取和写入数据。

公开(公告)号：US6122712A

公开(公告)日：2000-09-19

申请号：US946061

申请日：1997-10-07

申请人： Sunao Torii

发明人： Sunao Torii

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177 ,  G06F12/12 ,  G06F12/16

CPC分类号： G06F12/0842 ,  G06F12/0828

摘要： Disclosed is a cache coherency controller used in a multi-processor system. The cache coherency controller reflects a cache line including data produced by a preceding thread to a cache line including data produced by a succeeding thread. On the other hand, the cache coherency controller prevents a cache line including data produced by the succeeding thread from being reflected to the cache line including data produced by the preceding thread. The cache coherency controller maintains a sequential order (relationship) among threads based on a thread sequence information table and thereby maintains data anti-dependence.

摘要翻译： 公开了一种在多处理器系统中使用的高速缓存一致性控制器。 高速缓存一致性控制器将包括由前一个线程产生的数据的高速缓存行反映到包括后续线程产生的数据的高速缓存行。 另一方面，高速缓存一致性控制器防止包括后续线程产生的数据的高速缓存行被反映到包括前一线程产生的数据的高速缓存行。 高速缓存一致性控制器基于线程序列信息表维护线程之间的顺序（关系），从而保持数据反依赖性。

公开(公告)号：US20110026405A1

公开(公告)日：2011-02-03

申请号：US12935035

申请日：2009-04-30

申请人： Masamichi Takagi ,  Sunao Torii

发明人： Masamichi Takagi ,  Sunao Torii

IPC分类号： H04L12/56 ,  H04L12/26

CPC分类号： H04L45/00 ,  H04L45/60 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251

摘要： A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing.

摘要翻译： 路由器包括：飞行到达时间管理部，其记录作为第一次接收分组的时间的飞行到达时间，从在第一次发送之前发送的控制分组获取的分组的发送间隔 分组和控制分组的输入和输出通道，并且需要用于输出通道的横截面部分，在该输出通道之前，应该在该飞行器到达时间之前输出该分组; 开关分配单元，对所述输出通道请求进行仲裁，并进行输入/输出连接关系设定处理; 以及开关分配验证部，其验证输入/输出连接关系设置处理的结果是否与分组的实际路由一致。 横杆部分使用输入/输出连接关系处理的结果来执行到达的分组的切换。

公开(公告)号：US20100321051A1

公开(公告)日：2010-12-23

申请号：US12525953

申请日：2008-01-25

申请人： Noriaki Suzuki ,  Sunao Torii

发明人： Noriaki Suzuki ,  Sunao Torii

IPC分类号： G01R31/3187

CPC分类号： G06F11/3636 ,  G06F11/3648

摘要： A main functional structure executes continuous predetermined operations to continuously generate events associated with the operations. A debug/trace circuit compares an event occurring at the main functional structure with detection condition indicating information of one entry in a control information list, and executes the operation designated by operation indicating information paired with the detection condition indicating information in accordance with the result of the comparison. The debug/trace circuit continuously performs this in accordance with the control information list to identify the event.

摘要翻译： 主要功能结构执行连续的预定操作，以连续地生成与操作有关的事件。 调试/跟踪电路将主功能结构中发生的事件与指示控制信息列表中的一个条目的信息的检测条件进行比较，并且根据检测条件指示信息的结果执行指示与检测条件指示信息配对的操作的操作 比较。 调试/跟踪电路根据控制信息列表连续执行此操作以识别事件。

公开(公告)号：US20100183015A1

公开(公告)日：2010-07-22

申请号：US12663474

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04L12/56

CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

公开(公告)号：US20100172366A1

公开(公告)日：2010-07-08

申请号：US12663477

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04L12/56

CPC分类号： G06F15/16 ,  G06F21/50 ,  G06F21/577 ,  H04L29/06

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

公开(公告)号：US07266643B2

公开(公告)日：2007-09-04

申请号：US10879855

申请日：2004-06-28

申请人： Sunao Torii

发明人： Sunao Torii

IPC分类号： G06F13/16

CPC分类号： G06F3/147 ,  G06F12/08 ,  G06F12/0875 ,  G06F2212/251 ,  G06F2212/253 ,  G09G5/363 ,  G09G5/399 ,  G09G2360/121 ,  Y02D10/13

摘要： The data processing unit uses, for predetermined information processing, a series of data read by uniformly accessing a predetermined address range of the external storage device through the external interface. The determination unit determines whether to write the data read from the external storage device by the data processing unit to the internal storage unit or not and writes, to the internal storage unit, data determined to be written to the internal storage unit. When again reading data within the same address range of the external storage device, the data processing unit alternatively reads data from the internal storage unit.

摘要翻译： 数据处理单元通过外部接口统一访问外部存储装置的预定地址范围，对预定信息处理使用一系列数据。 确定单元确定是否将数据处理单元从外部存储装置读取的数据写入内部存储单元，并向内部存储单元写入确定写入内部存储单元的数据。 当再次读取外部存储装置的相同地址范围内的数据时，数据处理单元从内部存储单元交替地读取数据。

公开(公告)号：US08738881B2

公开(公告)日：2014-05-27

申请号：US12865781

申请日：2009-02-06

申请人： Noriaki Suzuki ,  Sunao Torii ,  Junji Sakai

发明人： Noriaki Suzuki ,  Sunao Torii ,  Junji Sakai

IPC分类号： G06F12/08 ,  G06F3/06

CPC分类号： G06F3/0644 ,  G06F11/3419 ,  G06F11/3466 ,  G06F12/0802 ,  G06F2201/88 ,  G06F2201/885

摘要： Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small. The performance optimization system includes: a required-period-of-time measurement unit that measures a required period of time concerning a to-be-observed access; a required-period-of-time table holding unit that holds a required-period-of-time table that consists of a plurality of table entries in which stored are measured values of the required period of time for each of classification regions produced by dividing a memory region for each of types based on the to-be-observed access to store a measured value of the required period of time; a table entry selection unit that makes a selection as to in which table entry, out of a plurality of table entries for each of the classification regions that make up the required-period-of-time table, the measured value of the required period of time is stored on the basis of the to-be-observed access; and a cache miss observation unit that detects the occurrence of a cache miss associated with the to-be-observed access.

摘要翻译： 提供了一种性能优化系统，可以识别即使高速缓存未命中的数量较小，对性能的影响也很大的情况。 绩效优化系统包括：一个需要的时间测量单元，用于测量与待观察的访问有关的所需时间; 所需时间表保持单元，其保存由存储的多个表条目组成的所需时间周期表，所述时间表存储的是通过划分产生的每个分类区域所需的时间段的测量值 基于待观察访问的每种类型的存储区域来存储所需时间段的测量值; 表格条目选择单元，对于构成所需时间表的每个分类区域的多个表条目中的哪个表条目进行选择所需时间段的测量值 时间根据被观察的访问存储; 以及高速缓存未命中观察单元，其检测与所述待观察访问相关联的高速缓存未命中的发生。

公开(公告)号：US08125364B2

公开(公告)日：2012-02-28

申请号：US12673459

申请日：2008-07-24

申请人： Sunao Torii

发明人： Sunao Torii

IPC分类号： H03M7/34

CPC分类号： H03M7/30

摘要： A compression engine starts compressing data by a preset first compression rule, compresses the following data by a second compression rule when the characteristics of the data satisfy a predetermined switching condition, and returns to the first compression rule when the characteristics of the data do not satisfy the switching condition to compress the data and the following data. A decompression engine starts decompressing compressed data by a first decompression rule corresponding to the first compression rule, decompresses the following compressed data by a second decompression rule corresponding to the second compression rule when the characteristics of the data after decompression satisfy the switching condition, and returns to the first decompression rule when the characteristics of the data after decompression do not satisfy the switching condition to decompress the data and the following compressed data.

摘要翻译： 压缩引擎以预设的第一压缩规则开始压缩数据，当数据的特性满足预定的切换条件时，通过第二压缩规则压缩以下数据，并且当数据的特性不满足时返回到第一压缩规则 用于压缩数据的切换条件和以下数据。 解压缩引擎通过与第一压缩规则相对应的第一解压缩规则开始对压缩数据进行解压缩，当解压缩后的数据的特性满足切换条件时，通过对应于第二压缩规则的第二解压缩规则解压缩以下压缩数据，并返回 当解压缩后的数据的特性不满足解压缩数据的切换条件和下列压缩数据时，到第一解压规则。

公开(公告)号：US20110199241A1

公开(公告)日：2011-08-18

申请号：US12673459

申请日：2008-07-24

申请人： Sunao Torii

发明人： Sunao Torii

IPC分类号： H03M7/30

CPC分类号： H03M7/30

摘要： A compression engine starts compressing data by a preset first compression rule, compresses the following data by a second compression rule when the characteristics of the data satisfy a predetermined switching condition, and returns to the first compression rule when the characteristics of the data do not satisfy the switching condition to compress the data and the following data. A decompression engine starts decompressing compressed data by a first decompression rule corresponding to the first compression rule, decompresses the following compressed data by a second decompression rule corresponding to the second compression rule when the characteristics of the data after decompression satisfy the switching condition, and returns to the first decompression rule when the characteristics of the data after decompression do not satisfy the switching condition to decompress the data and the following compressed data.

摘要翻译： 压缩引擎以预设的第一压缩规则开始压缩数据，当数据的特性满足预定的切换条件时，通过第二压缩规则压缩以下数据，并且当数据的特性不满足时返回到第一压缩规则 用于压缩数据的切换条件和以下数据。 解压缩引擎通过与第一压缩规则相对应的第一解压缩规则开始对压缩数据进行解压缩，当解压缩后的数据的特性满足切换条件时，通过对应于第二压缩规则的第二解压缩规则解压缩以下压缩数据，并返回 当解压缩后的数据的特性不满足解压缩数据的切换条件和下列压缩数据时，到第一解压规则。