公开(公告)号：US10504469B2

公开(公告)日：2019-12-10

申请号：US15768948

申请日：2017-10-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seung Woo Han ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng ,  Mingfu Han ,  Zhichong Wang ,  Lijun Yuan ,  Yun Sik Im ,  Jing Lv ,  Yinglong Huang ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/3266 ,  G09G3/20 ,  G11C19/18

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

公开(公告)号：US10475409B2

公开(公告)日：2019-11-12

申请号：US15796463

申请日：2017-10-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Xing Yao ,  Guangliang Shang ,  Haoliang Zheng ,  Seung-Woo Han ,  Jiha Kim ,  Lijun Yuan ,  Zhichong Wang

IPC: G11C19/00 ,  G09G3/36 ,  G06F3/041 ,  G11C19/28

Abstract: The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.

公开(公告)号：US10276087B2

公开(公告)日：2019-04-30

申请号：US15326370

申请日：2015-12-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seung Woo Han ,  Mingfu Han ,  Haoliang Zheng ,  Yanfeng Wang

IPC: G09G3/20

Abstract: The present disclosure discloses a GOA unit driving circuit and a driving method thereof, a display panel and a display device. The disclosure relates to field of display technology, and solves the technical issue of increased power consumption of the display device due to the power consumption of the parasitic capacitance existing in the transistors in the GOA unit. The GOA unit driving circuit comprises a plurality of sets of GOA units, each of which includes at least one GOA unit; a plurality of clock selecting units, which are in one-to-one correspondence with the plurality of sets of GOA units, and each clock selecting unit is connected to a corresponding set of GOA units and connected to one of a plurality of clock signal terminals and at least one of a plurality of clock selection signal terminals, respectively. An intersection of any two sets of GOA units in the plurality of sets of GOA unit is an empty set, and each clock selecting unit transmits a signal of the clock signal terminal to which the clock selecting unit is connected to the corresponding set of GOA units, under control of a signal of the at least one clock selection signal terminal to which the clock selecting unit is connected. The GOA unit driving circuit provided by the present disclosure may be applied to a display device.

公开(公告)号：US10269290B2

公开(公告)日：2019-04-23

申请号：US15680416

申请日：2017-08-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Mingfu Han ,  Haoliang Zheng ,  Han-Seung- Woo ,  Im-Yun- Sik ,  Jing Lv ,  Yinglong Huang ,  Jun-Jung- Mok ,  Xue Dong ,  Zhichong Wang ,  Xing Yao ,  Lijun Yuan ,  Zhihe Jin

IPC: G09G3/36 ,  G09G3/20 ,  G11C19/28 ,  G09G3/3266

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

公开(公告)号：US20180301200A1

公开(公告)日：2018-10-18

申请号：US15520191

申请日：2016-11-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seungwoo Han ,  Mingfu Han ,  Haoliang Zheng ,  Xing Yao ,  Hyunsic Choi

IPC: G11C19/28 ,  G09G3/36

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2330/06

Abstract: The present application discloses a control circuit for controlling a noise reduction thin film transistor in a shift register unit. The control circuit includes a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register; a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.

公开(公告)号：US10096374B2

公开(公告)日：2018-10-09

申请号：US15539220

申请日：2016-11-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seungwoo Han ,  Haoliang Zheng ,  Xing Yao ,  Mingfu Han ,  Hyunsic Choi ,  Yunsik Im ,  Yinglong Huang ,  Jungmok Jun ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

公开(公告)号：US20180190180A1

公开(公告)日：2018-07-05

申请号：US15680416

申请日：2017-08-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Mingfu Han ,  Haoliang Zheng ,  Han-Seung- Woo ,  Im-Yun- Sik ,  Jing Lv ,  Yinglong Huang ,  Jun-Jung- Mok ,  Xue Dong ,  Zhichong Wang ,  Xing Yao ,  Lijun Yuan ,  Zhihe Jin

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/043 ,  G09G2330/02 ,  G11C19/28

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

公开(公告)号：US10002675B2

公开(公告)日：2018-06-19

申请号：US15504119

申请日：2016-08-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Seungwoo Han ,  Xing Yao ,  Hyunsic Choi ,  Guangliang Shang ,  Mingfu Han ,  Yunsik Im ,  Jungmok Jun ,  Xue Dong

IPC: G09G5/00 ,  G11C19/28 ,  G09G3/36 ,  G11C19/18 ,  H01L27/12

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251

Abstract: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.

公开(公告)号：US12274127B2

公开(公告)日：2025-04-08

申请号：US17615058

申请日：2021-02-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Dongni Liu ,  Minghua Xuan ,  Haoliang Zheng ,  Jiao Zhao

IPC: H10K59/121 ,  H10K59/131 ,  H10K59/30 ,  H10K59/12

Abstract: An array substrate is configured to carry a plurality of light emitting units with different light emitting colors. The array substrate includes a plurality of pixel driving circuits, a first voltage input line and a second voltage input line. The plurality of pixel driving circuits include at least one first driving circuit and at least one second driving circuit. The first voltage input line is coupled to the at least one first driving circuit, and is configured to transmit a first voltage to the at least one first driving circuit. The second voltage input line is coupled to the at least one second driving circuit, and is configured to transmit a second voltage to the at least one second driving circuit. The first voltage is different from the second voltage.

公开(公告)号：US12266747B2

公开(公告)日：2025-04-01

申请号：US17522282

申请日：2021-11-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiao Zhao ,  Haoliang Zheng ,  Li Xiao ,  Dongni Liu ,  Liang Chen ,  Hao Chen ,  Minghua Xuan

IPC: H01L33/62 ,  H01L33/00 ,  H01L33/38

Abstract: The present disclosure discloses a light-emitting substrate, a method for forming the light-emitting substrate and a display device. The light-emitting substrate includes: a base substrate; a first signal line located at one side of the base substrate; an insulation layer located at one side of the first signal line away from the base substrate; an electrode layer located at one side of the insulation layer away from the base substrate and including a first electrode terminal, a second electrode terminal and a second signal line, where the first electrode terminal is electrically connected to the first signal line via a first through hole penetrating the insulation layer; and at least one light-emitting element bound and connected to the first electrode terminal and the second electrode terminal.