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11.
公开(公告)号:US20210241673A1
公开(公告)日:2021-08-05
申请号:US16650306
申请日:2019-03-28
发明人: Peng LIU , Bailing LIU , Fuqiang LI , Zhichong WANG , Jing FENG , Xinglong LUAN
IPC分类号: G09G3/20
摘要: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a fist pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.
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公开(公告)号:US20170168616A1
公开(公告)日:2017-06-15
申请号:US15036924
申请日:2015-12-10
发明人: Jing FENG
CPC分类号: G06F3/0412 , C23C14/0036 , C23C14/083 , G06F3/044 , G06F2203/04103 , G06F2203/04111
摘要: The present application discloses a substrate comprising a peripheral region, wherein the peripheral region comprises a first light blocking layer and a metal light blocking layer sequentially on a base substrate along a direction away from the base substrate.
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公开(公告)号:US20220246460A1
公开(公告)日:2022-08-04
申请号:US17488538
申请日:2021-09-29
发明人: Guangcai YUAN , Haixu LI , Xin GU , Jing FENG
IPC分类号: H01L21/683 , H01L25/075 , H01L33/62 , B65G43/10
摘要: The disclosure provides an apparatus for transferring LED chips, including: first light source configured to generate and emit first light rays; first support structure configured to carry load substrate, load substrate including light-transmissive substrate and the LED chips fixed on side of the light-transmissive substrate away from first light source by dissociation adhesive; second support structure configured to carry to-be-transferred substrate on side of the LED chips away from light-transmissive substrate; and optical control mechanism on side of light-transmissive substrate away from the LED chips and configured to control propagation direction of first light rays that irradiate onto first radiation region of the optical control mechanism to form target light rays that irradiate onto target radiation region of load substrate, so that dissociation adhesive in target radiation region is dissociated to transfer LED chips in target radiation region to to-be-transferred substrate.
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公开(公告)号:US20220130310A1
公开(公告)日:2022-04-28
申请号:US17355954
申请日:2021-06-23
发明人: Zhichong WANG , Guangcai YUAN , Fuqiang LI , Liwei LIU , Jing FENG , Peng LIU , Xinglong LUAN
IPC分类号: G09G3/20
摘要: A gate driving circuit unit, a gate driving circuit and a display device are provided. The gate driving circuit unit includes a pull-up node noise-reduction circuit and a pull-up control circuit. The pull-up node noise-reduction circuit is electrically connected to an input end, a pull-down node and a pull-up node, and configured to control the pull-up node to be electrically connected to, or electrically disconnected from, the input end under the control of a potential at the pull-down node. The pull-up control circuit is electrically connected to the pull-up node and the input end, and configured to control the pull-up node to be electrically connected to the input end at an input stage.
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公开(公告)号:US20220130309A1
公开(公告)日:2022-04-28
申请号:US17355858
申请日:2021-06-23
发明人: Zhichong WANG , Guangcai YUAN , Fuqiang LI , Jing FENG , Xinglong LUAN , Peng LIU
IPC分类号: G09G3/20
摘要: A gate driving unit includes: a pull-up node denoising circuit; a pull-down node control circuit; a pull-up node control circuit; and an energy storage circuit. The pull-up node denoising circuit is configured to, under control of a potential of the pull-down node, control coupling or discoupling between the first pull-up node and the input terminal. The pull-down node control circuit is configured to, under control of a control voltage, control the potential of the pull-down node; under control of a potential of the second pull-up node, control coupling or discoupling between the pull-down node and the input terminal. The pull-up node control circuit is configured to, under control of an anti-leakage control voltage, control coupling or discoupling between the first pull-up node and the second pull-up node, and configured to maintain the potential of the second pull-up node. The energy storage circuit is configured to store electric energy.
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公开(公告)号:US20210166602A1
公开(公告)日:2021-06-03
申请号:US17051738
申请日:2020-01-21
发明人: Zhichong WANG , Fuqiang LI , Jing FENG , Peng LIU , Xinglong LUAN
摘要: A shift register includes a first transistor, a second transistor, a pull-up node and a switch sub-circuit. A control electrode of the first transistor is connected to a signal input terminal, a first electrode of the first transistor is connected to a first voltage terminal, and a second electrode of the first transistor is connected to a first control node. A control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second voltage terminal, and a second electrode of the second transistor is connected to the first control node. The switching sub-circuit is connected to the first control node and the pull-up node, and is configured to control a line between the first control node and the pull-up node to be closed and opened.
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公开(公告)号:US20180308958A1
公开(公告)日:2018-10-25
申请号:US15329212
申请日:2016-07-25
发明人: Shi SHU , Jing FENG , Chuanxiang XU , Xiaolong HE , Jiushi WANG
IPC分类号: H01L29/66 , H01L27/12 , H01L29/786 , H01L21/02
CPC分类号: H01L29/66969 , H01L21/02488 , H01L21/02565 , H01L21/02631 , H01L27/1225 , H01L27/1262 , H01L27/127 , H01L29/7869 , H01L29/78696
摘要: A method for manufacturing an array substrate, an array substrate and a display panel are provided. The method includes forming patterns of a gate metal layer and a gate insulating layer successively on a base plate, forming a pattern of a semiconductor layer, where the pattern of the semiconductor layer comprises a pattern of an active region and a pattern of a pixel electrode region, the semiconductor layer comprises an insulative oxide layer and a semiconductive oxide layer stacked on the insulative oxide layer, and the insulative oxide layer is located between the gate insulating layer and the semiconductive oxide layer, forming a pattern of a source and drain metal layer, and subjecting the semiconductive oxide layer in the pixel electrode region to plasma treatment, to convert the semiconductive oxide layer in the pixel electrode region into a conductor.
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