公开(公告)号：US07573766B2

公开(公告)日：2009-08-11

申请号：US11898125

申请日：2007-09-10

申请人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

发明人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

IPC分类号： G11C29/00

CPC分类号： G11C13/0004 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

摘要： Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.

摘要翻译： 提供了一种测试相变随机存取存储器（PRAM）的方法。 该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线， 所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压 线。

公开(公告)号：US07450415B2

公开(公告)日：2008-11-11

申请号：US11640956

申请日：2006-12-19

申请人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

发明人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

IPC分类号： G11C11/00

CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.

摘要翻译： 提供了相变存储器件。 相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第 多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及 行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

公开(公告)号：US20080062741A1

公开(公告)日：2008-03-13

申请号：US11898125

申请日：2007-09-10

申请人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

发明人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

IPC分类号： G11C29/44

CPC分类号： G11C13/0004 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

摘要： Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.

摘要翻译： 提供了一种测试相变随机存取存储器（PRAM）的方法。 该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线， 所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压 线。

公开(公告)号：US20070153616A1

公开(公告)日：2007-07-05

申请号：US11640956

申请日：2006-12-19

申请人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

发明人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.

摘要翻译： 提供了相变存储器件。 相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第 多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及 行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

公开(公告)号：US07688620B2

公开(公告)日：2010-03-30

申请号：US11834843

申请日：2007-08-07

申请人： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

发明人： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.

摘要翻译： 在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作 并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

公开(公告)号：US07283387B2

公开(公告)日：2007-10-16

申请号：US11316256

申请日：2005-12-23

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

摘要翻译： 相变存储器件包括包括多个相变存储器单元的存储器阵列，每个相变存储单元包括相变材料和二极管，多个列选择晶体管将连接到相变存储单元的位线连接到相应的 数据线和将数据线连接到读出放大器单元的控制节点。 在写入操作模式中，通过升压第一电压获得的控制电压分别施加到列选择晶体管的控制节点和栅极，并且将接地电压施加到所选择的一个相变存储单元的字线。 在备用模式中，连接到存储器阵列的相变存储单元的字线和位线保持在相同的电压。 根据相变存储器件及其驱动方法，在写入操作模式中向写入驱动器，列解码器和行解码器提供足够的写入电压，并且将较低的电压施加到写入驱动器，列 解码器和行解码器处于读取操作模式和待机模式，从而降低电流消耗并提高操作可靠性。

公开(公告)号：US20070058425A1

公开(公告)日：2007-03-15

申请号：US11316256

申请日：2005-12-23

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

公开(公告)号：US20070014150A1

公开(公告)日：2007-01-18

申请号：US11319601

申请日：2005-12-29

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C13/0038 ,  G11C5/145 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009

摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.

摘要翻译： 一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。 写升压电路升压第一电压并响应于第一操作模式中的控制信号输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且 第三操作模式。 写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

公开(公告)号：US06816429B2

公开(公告)日：2004-11-09

申请号：US10268380

申请日：2002-10-09

申请人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

发明人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

IPC分类号： G11C700

CPC分类号： G11C29/50

摘要： An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.

摘要翻译： 提供了能够用AC应力进行老化测试的集成电路和使用其的测试方法。 集成电路包括地址转换装置和数据产生装置。 地址变换装置变换选择的存储器件的地址，并响应于时钟信号产生地址信号。 数据产生装置产生响应于时钟信号在第一状态和第二状态之间交替的数据信号，并将数据信号提供给选择的存储器件。 集成电路包括用于在测试期间将测试电源线连接到正常供电线的开关，并且响应于控制信号在正常操作期间从正常供电线截取测试电源线。 本发明的集成电路允许通过对所有的存储器件顺序并重复地施加AC应力来进行晶片老化测试。

公开(公告)号：US06490223B1

公开(公告)日：2002-12-03

申请号：US09614783

申请日：2000-07-12

申请人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

发明人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

IPC分类号： G11C800

CPC分类号： G11C29/50

摘要： An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory cell selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory cell. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory cells.

摘要翻译： 提供了能够用AC应力进行老化测试的集成电路和使用其的测试方法。 集成电路包括地址转换装置和数据产生装置。 地址变换装置对所选存储单元的地址进行变换，并根据时钟信号生成地址信号。 数据产生装置产生响应于时钟信号在第一状态和第二状态之间交替的数据信号，并将数据信号提供给选定的存储单元。 集成电路包括用于在测试期间将测试电源线连接到正常供电线的开关，并且响应于控制信号在正常操作期间从正常供电线截取测试电源线。 本发明的集成电路允许通过对所有的存储单元顺序并重复地施加AC应力来进行晶片老化测试。