公开(公告)号：US20070014150A1

公开(公告)日：2007-01-18

申请号：US11319601

申请日：2005-12-29

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C13/0038 ,  G11C5/145 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009

摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.

摘要翻译： 一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。 写升压电路升压第一电压并响应于第一操作模式中的控制信号输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且 第三操作模式。 写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

公开(公告)号：US07457151B2

公开(公告)日：2008-11-25

申请号：US11319601

申请日：2005-12-29

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C5/145 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009

摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.

摘要翻译： 一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。 写升压电路响应于第一操作模式中的控制信号而升高第一电压并输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且 第三操作模式。 写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

公开(公告)号：US07283387B2

公开(公告)日：2007-10-16

申请号：US11316256

申请日：2005-12-23

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

摘要翻译： 相变存储器件包括包括多个相变存储器单元的存储器阵列，每个相变存储单元包括相变材料和二极管，多个列选择晶体管将连接到相变存储单元的位线连接到相应的 数据线和将数据线连接到读出放大器单元的控制节点。 在写入操作模式中，通过升压第一电压获得的控制电压分别施加到列选择晶体管的控制节点和栅极，并且将接地电压施加到所选择的一个相变存储单元的字线。 在备用模式中，连接到存储器阵列的相变存储单元的字线和位线保持在相同的电压。 根据相变存储器件及其驱动方法，在写入操作模式中向写入驱动器，列解码器和行解码器提供足够的写入电压，并且将较低的电压施加到写入驱动器，列 解码器和行解码器处于读取操作模式和待机模式，从而降低电流消耗并提高操作可靠性。

公开(公告)号：US20070058425A1

公开(公告)日：2007-03-15

申请号：US11316256

申请日：2005-12-23

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

公开(公告)号：US07397681B2

公开(公告)日：2008-07-08

申请号：US11348432

申请日：2006-02-06

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

IPC分类号： G11C27/00

CPC分类号： G11C11/5678 ,  G11C13/0004

摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

公开(公告)号：US20060215440A1

公开(公告)日：2006-09-28

申请号：US11348432

申请日：2006-02-06

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0004

摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

公开(公告)号：US07859882B2

公开(公告)日：2010-12-28

申请号：US11844511

申请日：2007-08-24

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2213/79

摘要： A resistive memory device is provided. The resistive memory device includes word lines arranged in M rows, bit lines arranged in N columns, local source lines arranged in M/2 rows, and resistive memory cells arranged in M rows and N columns. Each of the resistive memory cells includes a resistance variable element having a first electrode connected to a corresponding bit line, and a cell transistor having a first terminal connected to a second electrode of the resistance variable element, a second terminal connected to a corresponding local source line, and a control terminal connected to a corresponding word line. The local source line is commonly connected to the second terminals of the cell transistors of the two neighboring rows.

摘要翻译： 提供了一种电阻式存储器件。 电阻式存储装置包括排列成M行的字线，以N列排列的位线，以M / 2行排列的局部源极线以及布置成M行N列的电阻存储单元。 每个电阻存储单元包括电阻可变元件，电阻可变元件具有连接到对应的位线的第一电极，以及单元晶体管，其具有连接到电阻可变元件的第二电极的第一端子，连接到相应的本地源极的第二端子 线路和连接到相应字线的控制终端。 本地源极线通常连接到两个相邻行的单元晶体管的第二端子。

公开(公告)号：US20070195591A1

公开(公告)日：2007-08-23

申请号：US11790444

申请日：2007-04-25

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C11/00

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.

摘要翻译： 半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧 第一面相反 该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接 。 该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

公开(公告)号：US20060285380A1

公开(公告)日：2006-12-21

申请号：US11315130

申请日：2005-12-23

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： A phase change memory device includes a phase change memory cell block having alternating odd-numbered and even-numbered local bit lines, a global bit line, a plurality of first bit line selection circuits, and a plurality of second bit line selection circuits. The plurality of first bit line selection circuits are located at a first side of the phase change memory cell block and selectively connect respective odd-numbered local bit lines to the global bit line. The plurality of second bit line selection circuits are located at second side of the phase change memory cell block (opposite the first side) and selectively connect respective even-numbered local bit lines to the global bit line.

摘要翻译： 相变存储器件包括具有交替的奇数和偶数编号的局部位线，全局位线，多个第一位线选择电路和多个第二位线选择电路的相变存储器单元块。 多个第一位线选择电路位于相变存储单元块的第一侧，并且选择性地将各自的奇数本地位线连接到全局位线。 多个第二位线选择电路位于相变存储单元块的第二侧（与第一侧相反），并且选择性地将各偶数的局部位线连接到全局位线。

公开(公告)号：US20050052904A1

公开(公告)日：2005-03-10

申请号：US10929511

申请日：2004-08-30

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak

IPC分类号： G11C13/02 ,  G11C11/00 ,  G11C16/20

CPC分类号： G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

摘要： A firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation are described. The phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block. The driving unit applies a firing current to the memory cell array blocks in response to the firing mode signal. According to the phase change memory device and the initial firing method, the time taken to perform the initial firing operation can be reduced. In addition, since the numbers of the needed signals are minimized, a large number of chips on a single wafer can be simultaneously tested.

摘要翻译： 描述能够有效地执行点火操作的相变存储器件和相变存储器的点火方法。 相变存储器件包括多个存储单元阵列块，计数器时钟生成单元，解码单元和驱动单元。 每个存储单元阵列块具有相变存储单元。 计数器时钟产生单元响应于外部时钟信号和触发模式信号输出第一至第三计数器时钟信号，其中第一至第三计数器时钟信号具有不同的周期。 解码单元响应于第一至第三计数器时钟信号输出选择多个存储单元阵列块中的一个的块地址，使得能够选择的存储单元阵列块的字线的字线地址和冗余字 行地址，其使能所选存储单元阵列块的冗余字线。 驱动单元响应于点火模式信号向存储单元阵列块施加点火电流。 根据相变存储器件和初始烧制方法，可以减少执行初始点火操作所花费的时间。 此外，由于所需信号的数量最小化，可以同时测试单个晶片上的大量芯片。