公开(公告)号：US07670876B2

公开(公告)日：2010-03-02

申请号：US12153584

申请日：2008-05-21

申请人： Mon-Chin Tsai

发明人： Mon-Chin Tsai

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L25/16 ,  H01L25/0657 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599

摘要： An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

摘要翻译： 提供了一种通过倒装芯片连接的嵌入式无源部件的集成电路器件，其包括倒装芯片和虚设芯片。 虚拟芯片至少包括嵌入式无源元件，多个再分配迹线和多个倒装芯片焊盘。 倒装芯片比虚拟芯片小，并且用倒装芯片焊盘安装在虚设芯片的表面上。 嵌入式无源元件经由再分配迹线和倒装芯片焊盘与倒装芯片电连接。 在虚拟芯片的表面的周边区域配置有多个焊锡球。

公开(公告)号：US20060197191A1

公开(公告)日：2006-09-07

申请号：US11164970

申请日：2005-12-13

申请人： Mon-Chin Tsai ,  Chi-Yu Wang ,  Jian-Wen Lo ,  Shao-Wen Fu

发明人： Mon-Chin Tsai ,  Chi-Yu Wang ,  Jian-Wen Lo ,  Shao-Wen Fu

IPC分类号： H01L23/58

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00

摘要： A chip structure comprising a substrate, a circuitry unit, a plurality of bonding pads, a first passivation layer and a redistribution layer is provided. The circuitry unit is disposed on the substrate, and the bonding pads are disposed on the circuitry unit. Moreover, the first passivation layer is disposed on the circuitry unit and exposes the bonding pads. The redistribution layer of a Ti/Cu/Ti multi-layered structure is disposed on the first passivation layer, and is electrically connected with the bonding pads. In addition, the redistribution layer of a Ti/Cu/Ti multi-layered structure has excellent conductivity such that electrical characteristics of the chip structure are enhanced effectively.

摘要翻译： 提供了包括基板，电路单元，多个接合焊盘，第一钝化层和再分配层的芯片结构。 电路单元设置在基板上，并且接合焊盘设置在电路单元上。 此外，第一钝化层设置在电路单元上并且暴露接合焊盘。 Ti / Cu / Ti多层结构的再分布层设置在第一钝化层上，并与接合焊盘电连接。 此外，Ti / Cu / Ti多层结构的再分布层具有优异的导电性，使得芯片结构的电特性得到有效的提高。

公开(公告)号：US20060113532A1

公开(公告)日：2006-06-01

申请号：US10996365

申请日：2004-11-26

申请人： Mon-Chin Tsai ,  Xinghua Pu ,  Ning Jiang ,  Jun He

发明人： Mon-Chin Tsai ,  Xinghua Pu ,  Ning Jiang ,  Jun He

IPC分类号： H01L23/58

CPC分类号： G01R31/025 ,  H01L22/34

摘要： A test structure for testing a multidirectional current leakage path. A first doped region of a first conductivity is in the first well of the first conductivity in a substrate, in which the first doped region has a dopant concentration higher than the first well has. A first contact is on the first doped region and contacts the first doped region. The first contact has first and second portions respectively parallel to the first and second directions. A plurality of second doped regions of a second conductivity are in the first well and isolated from the first doped region. In a third direction, the second regions are adjacent to each another and isolate the first portion from the second portion. A plurality of second contacts are on the second doped regions and each one is corresponding to each the second doped region. With a relative shift between the first contact and the second doped region, the partial overlap is used in the test of a multidirectional leakage path.

摘要翻译： 用于测试多向电流泄漏路径的测试结构。 第一导电性的第一掺杂区域在衬底中位于第一导电性的第一阱中，其中第一掺杂区域具有高于第一阱的掺杂剂浓度。 第一接触在第一掺杂区域上并接触第一掺杂区域。 第一触点具有分别平行于第一和第二方向的第一和第二部分。 具有第二导电性的多个第二掺杂区域位于第一阱中并与第一掺杂区隔离。 在第三方向上，第二区域彼此相邻并且将第一部分与第二部分隔离。 多个第二触点位于第二掺杂区域上，并且每个第二触点对应于每个第二掺杂区域。 通过第一接触和第二掺杂区域之间的相对移动，在多向泄漏路径的测试中使用部分重叠。

公开(公告)号：US07332741B2

公开(公告)日：2008-02-19

申请号：US10996365

申请日：2004-11-26

申请人： Mon-Chin Tsai ,  Xinghua Pu ,  Ning Jiang ,  Jun He

发明人： Mon-Chin Tsai ,  Xinghua Pu ,  Ning Jiang ,  Jun He

IPC分类号： H01L29/40

CPC分类号： G01R31/025 ,  H01L22/34

摘要： A test structure for testing a multidirectional current leakage path. A first doped region of a first conductivity is in the first well of the first conductivity in a substrate, in which the first doped region has a dopant concentration higher than the first well has. A first contact is on the first doped region and contacts the first doped region. The first contact has first and second portions respectively parallel to the first and second directions. A plurality of second doped regions of a second conductivity are in the first well and isolated from the first doped region. In a third direction, the second regions are adjacent to each another and isolate the first portion from the second portion. A plurality of second contacts are on the second doped regions and each one is corresponding to each the second doped region. With a relative shift between the first contact and the second doped region, the partial overlap is used in the test of a multidirectional leakage path.

摘要翻译： 用于测试多向电流泄漏路径的测试结构。 第一导电性的第一掺杂区域在衬底中位于第一导电性的第一阱中，其中第一掺杂区域具有高于第一阱的掺杂剂浓度。 第一接触在第一掺杂区域上并接触第一掺杂区域。 第一触点具有分别平行于第一和第二方向的第一和第二部分。 具有第二导电性的多个第二掺杂区域位于第一阱中并与第一掺杂区隔离。 在第三方向上，第二区域彼此相邻并且将第一部分与第二部分隔离。 多个第二触点位于第二掺杂区域上，并且每个第二触点对应于每个第二掺杂区域。 通过第一接触和第二掺杂区域之间的相对移动，在多向泄漏路径的测试中使用部分重叠。

公开(公告)号：US20060199306A1

公开(公告)日：2006-09-07

申请号：US11306054

申请日：2005-12-15

申请人： Mon-Chin Tsai ,  Jian-Wen Lo ,  Shao-Wen Fu ,  Chi-Yu Wang

发明人： Mon-Chin Tsai ,  Jian-Wen Lo ,  Shao-Wen Fu ,  Chi-Yu Wang

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05099

摘要： A chip structure and the manufacturing process thereof are provided. The feature of the present application is that the chip structure has a first passivation layer covering a substrate of the chip and exposing each of bonding pads and a portion of the substrate surface, and a second passivation layer covering the sidewalls of the first passivation layer and the portion of substrate surface exposed by the first passivation layer, to prevent moisture infiltration from the edge of the substrate. Therefore, the reliability of the chip structure is enhanced.

摘要翻译： 提供了芯片结构及其制造方法。 本申请的特征在于，芯片结构具有覆盖芯片的衬底的第一钝化层和暴露每个焊盘和衬底表面的一部分，以及覆盖第一钝化层的侧壁的第二钝化层和 由第一钝化层暴露的衬底表面的部分，以防止水分从衬底的边缘渗透。 因此，提高了芯片结构的可靠性。