公开(公告)号：US20060199306A1

公开(公告)日：2006-09-07

申请号：US11306054

申请日：2005-12-15

申请人： Mon-Chin Tsai ,  Jian-Wen Lo ,  Shao-Wen Fu ,  Chi-Yu Wang

发明人： Mon-Chin Tsai ,  Jian-Wen Lo ,  Shao-Wen Fu ,  Chi-Yu Wang

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05099

摘要： A chip structure and the manufacturing process thereof are provided. The feature of the present application is that the chip structure has a first passivation layer covering a substrate of the chip and exposing each of bonding pads and a portion of the substrate surface, and a second passivation layer covering the sidewalls of the first passivation layer and the portion of substrate surface exposed by the first passivation layer, to prevent moisture infiltration from the edge of the substrate. Therefore, the reliability of the chip structure is enhanced.

摘要翻译： 提供了芯片结构及其制造方法。 本申请的特征在于，芯片结构具有覆盖芯片的衬底的第一钝化层和暴露每个焊盘和衬底表面的一部分，以及覆盖第一钝化层的侧壁的第二钝化层和 由第一钝化层暴露的衬底表面的部分，以防止水分从衬底的边缘渗透。 因此，提高了芯片结构的可靠性。

公开(公告)号：US20060197191A1

公开(公告)日：2006-09-07

申请号：US11164970

申请日：2005-12-13

申请人： Mon-Chin Tsai ,  Chi-Yu Wang ,  Jian-Wen Lo ,  Shao-Wen Fu

发明人： Mon-Chin Tsai ,  Chi-Yu Wang ,  Jian-Wen Lo ,  Shao-Wen Fu

IPC分类号： H01L23/58

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00

摘要： A chip structure comprising a substrate, a circuitry unit, a plurality of bonding pads, a first passivation layer and a redistribution layer is provided. The circuitry unit is disposed on the substrate, and the bonding pads are disposed on the circuitry unit. Moreover, the first passivation layer is disposed on the circuitry unit and exposes the bonding pads. The redistribution layer of a Ti/Cu/Ti multi-layered structure is disposed on the first passivation layer, and is electrically connected with the bonding pads. In addition, the redistribution layer of a Ti/Cu/Ti multi-layered structure has excellent conductivity such that electrical characteristics of the chip structure are enhanced effectively.

摘要翻译： 提供了包括基板，电路单元，多个接合焊盘，第一钝化层和再分配层的芯片结构。 电路单元设置在基板上，并且接合焊盘设置在电路单元上。 此外，第一钝化层设置在电路单元上并且暴露接合焊盘。 Ti / Cu / Ti多层结构的再分布层设置在第一钝化层上，并与接合焊盘电连接。 此外，Ti / Cu / Ti多层结构的再分布层具有优异的导电性，使得芯片结构的电特性得到有效的提高。

公开(公告)号：US20090127686A1

公开(公告)日：2009-05-21

申请号：US11984781

申请日：2007-11-21

申请人： Wen-Kun Yang ,  Chi-Yu Wang ,  Hsien-Wen Hsu

发明人： Wen-Kun Yang ,  Chi-Yu Wang ,  Hsien-Wen Hsu

IPC分类号： H01L23/488 ,  H01L21/58

CPC分类号： H01L24/82 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： The present invention disclosed a first multi-die package structure for semiconductor devices, the structure comprises a substrate having die receiving window and inter-connecting through holes formed therein; a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within the die receiving window, wherein the first multi-die package includes first level contact pads formed under the first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of the first level semiconductor die; a second level contact pads formed on the second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of the second level semiconductor die; and conductive bumps formed under the first level build up layer.

摘要翻译： 本发明公开了一种用于半导体器件的第一多管芯封装结构，该结构包括具有管接收窗口和形成在其中的互连通孔的衬底; 第一级半导体管芯，其通过背对背方案形成在第二级半导体管芯下方并且在管芯接收窗内，其中第一多管芯封装包括形成在第一级半导体管芯下方的第一级接触焊盘，其具有第一级构建 形成在其下方以耦合到第一级半导体管芯的第一焊盘; 形成在所述第二级半导体管芯上的第二级接触焊盘，其上形成有第二级构建层，以耦合到所述第二级半导体管芯的第二接合焊盘; 以及形成在第一层建立层下面的导电凸块。

公开(公告)号：US07071544B2

公开(公告)日：2006-07-04

申请号：US10747055

申请日：2003-12-30

申请人： Chi-Yu Wang ,  Tai-Yuan Huang

发明人： Chi-Yu Wang ,  Tai-Yuan Huang

IPC分类号： H01L23/02

CPC分类号： H01L24/10 ,  H01L23/544 ,  H01L24/13 ,  H01L2223/54406 ,  H01L2223/5448 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166

摘要： A wafer level package mainly comprises a semiconductor wafer and a plurality of bonding pads disposed on the active surface of the wafer. It is characterized in that there is a protection layer formed on the back surface of the wafer, wherein the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the bonding pads. In such a manner, the protection layer will prevent the back surface of the wafer from being contaminated with the solder material. Moreover, when a UBM layer is further provided on the bonding pad, the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the UBM layer.

摘要翻译： 晶片级封装主要包括半导体晶片和设置在晶片的有源表面上的多个焊盘。 其特征在于，在晶片的背面形成有保护层，其中焊料材料与保护层的润湿性低于焊接材料与焊盘的润湿性。 以这种方式，保护层将防止晶片的背面被焊料材料污染。 此外，当在焊盘上进一步设置UBM层时，具有保护层的焊料材料的润湿性低于具有UBM层的焊料材料的润湿性。

公开(公告)号：US20070207606A1

公开(公告)日：2007-09-06

申请号：US11652085

申请日：2007-01-11

申请人： Chun-Chi Wang ,  Yao-Feng Huang ,  Chih-Hsing Chen ,  Chi-Yu Wang

发明人： Chun-Chi Wang ,  Yao-Feng Huang ,  Chih-Hsing Chen ,  Chi-Yu Wang

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  B23K1/203 ,  B23K1/206 ,  H01L24/13 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81011 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for removing residual flux applied to a wafer process is disclosed by the present invention, the method comprises the steps of: providing a wafer; forming a plurality of bumps on the surface of the wafer; coating flux on the surfaces of the bumps; reflowing the bumps; immersing the wafer in a cleaning solvent; cleaning the wafer by a plasma descum cleaning; rinsing the wafer; and drying the wafer.

摘要翻译： 通过本发明公开了一种去除施加到晶片工艺的剩余磁通的方法，该方法包括以下步骤：提供晶片; 在所述晶片的表面上形成多个凸起; 在凸块的表面上涂覆助焊剂; 回流颠簸 将晶片浸入清洗溶剂中; 通过等离子体清除清洁晶片; 冲洗晶片; 并干燥晶片。

公开(公告)号：US20060103020A1

公开(公告)日：2006-05-18

申请号：US11163815

申请日：2005-10-31

申请人： Ho-Ming Tong ,  Shin-Hua Chao ,  Chi-Yu Wang ,  Cherry Mercado Reyes

发明人： Ho-Ming Tong ,  Shin-Hua Chao ,  Chi-Yu Wang ,  Cherry Mercado Reyes

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

摘要： A circuit structure of a redistribution layer (RDL) is suitable for a chip to define the circuits and the contact window required by the following bump process. The RDL is disposed on the active surface of the chip. The circuit structure of the RDL mainly includes a first titanium layer, a second titanium layer and a conductive layer. Wherein, the conductive layer is made of aluminum; the first titanium layer and the second titanium layer cover the two surfaces of the conductive layer, respectively. The connectivity between the first titanium layer or the second titanium layer and a macromolecule polymer is stronger than the connectivity between the conductive layer and the macromolecule polymer, so that the peeling or crack caused by poor connectivity between the conductive layer and the adjacent dielectric layers are significantly improved thereby.

摘要翻译： 再分配层（RDL）的电路结构适用于芯片来定义随后的凸块工艺所需的电路和接触窗口。 RDL设置在芯片的有源表面上。 RDL的电路结构主要包括第一钛层，第二钛层和导电层。 其中，导电层由铝制成; 第一钛层和第二钛层分别覆盖导电层的两个表面。 第一钛层或第二钛层与高分子聚合物之间的连接性比导电层和高分子聚合物之间的连通性更强，导致导电层和相邻电介质层之间连接性差的剥离或裂纹是 从而显着改善。