公开(公告)号：US4812885A

公开(公告)日：1989-03-14

申请号：US81424

申请日：1987-08-04

申请人： Bert R. Riemenschneider

发明人： Bert R. Riemenschneider

IPC分类号： H01L29/788 ,  H01L29/92 ,  H01L29/78

CPC分类号： H01L28/40 ,  H01L29/7885 ,  Y10S257/90

摘要： An upstanding sidewall conductor (38) is formed in a via (30) that is made in a thick oxide layer (28) to expose a polysilicon gate electrode (22). A thin insulator layer (42) is deposited over the sidewall conductor layer (38) and a central region (32) of the polysilicon electrode (22). A second conductive layer (44) is deposited in the via (30) so as to be in registry with the upstanding sidewall conductor (38) and the central region (32) of the polysilicon electrode (22). In this way, the capacitive coupling between electrode (22) and electrode (44) is enhanced.

摘要翻译： 直立的侧壁导体（38）形成在通孔（30）中，所述通孔（30）由厚氧化物层（28）制成以暴露多晶硅栅电极（22）。 薄壁绝缘体层（42）沉积在侧壁导体层（38）和多晶硅电极（22）的中心区域（32）之上。 第二导电层（44）沉积在通路（30）中，以便与直立侧壁导体（38）和多晶硅电极（22）的中心区域（32）对准。 以这种方式，电极（22）和电极（44）之间的电容耦合被增强。

公开(公告)号：US5365105A

公开(公告)日：1994-11-15

申请号：US113507

申请日：1993-08-27

申请人： David K. Liu ,  Kueing-Long Chen ,  Bert R. Riemenschneider

发明人： David K. Liu ,  Kueing-Long Chen ,  Bert R. Riemenschneider

IPC分类号： H01L23/525 ,  H01L27/02 ,  H01L17/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A described embodiment of the present invention includes an anti-fuse comprising: a first conductive layer having a horizontal major surface and having a substantially vertical sidewall; a thick insulating layer formed on the horizontal major surface of the first conductive layer; a dielectric layer formed on the vertical sidewall; and a second conductive layer formed on the dielectric layer. In an additional embodiment, the first and/or second conductive layers comprise polycrystalline silicon and a conductive material selected from the group of titanium, tungsten, molybdenum, platinum, titanium silicide, tungsten silicide, molybdenum silicide, platinum silicide, titanium nitride and combinations thereof.

摘要翻译： 本发明的一个实施例包括一种抗熔丝，包括：第一导电层，其具有水平主表面并且具有基本垂直的侧壁; 形成在第一导电层的水平主表面上的厚绝缘层; 形成在垂直侧壁上的电介质层; 以及形成在所述电介质层上的第二导电层。 在另外的实施例中，第一和/或第二导电层包括多晶硅和选自钛，钨，钼，铂，硅化钛，硅化钨，硅化钼，硅化铂，氮化钛及其组合的导电材料 。

公开(公告)号：US4827323A

公开(公告)日：1989-05-02

申请号：US195346

申请日：1988-05-12

申请人： Howard L. Tigelaar ,  Bert R. Riemenschneider

发明人： Howard L. Tigelaar ,  Bert R. Riemenschneider

IPC分类号： H01L21/02 ,  H01L21/8229 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L29/78 ,  H01G4/06 ,  H01L23/48 ,  H01L27/02

CPC分类号： H01L27/1085 ,  H01L21/8229 ,  H01L27/10805 ,  H01L28/40 ,  H01L29/945

摘要： The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates. The area etched away is then filled with a suitable dielectric and a contact is made to the unetched interleaved plates. Thus a fully interleaved capacitor is provided using relatively simple fabrication techniques while still providing increased capacitance.

摘要翻译： 本发明提供了一种用于制造该结构的结构和方法，该结构在占用集成电路的最小表面积的同时提供了比现有技术更大的电容。 本发明通过交错多个电容器板来提供增加的电容，同时占据与现有技术的电容器相同的表面积，从而提供本发明提供的电容的一部分。 本发明通过提供一种电容器堆叠来制造，该电容器堆叠包括可被选择性蚀刻并由适当的介电材料分离的材料的交错板。 当一组交错板被蚀刻时，屏蔽该堆叠的一部分。 交错板的蚀刻部分由合适的电介质填充，并且与剩余的板接触。 然后将堆叠的不同部分暴露于蚀刻另一组交错板的蚀刻。 然后用合适的电介质填充被蚀刻的区域，并且对未蚀刻的交错板进行接触。 因此，使用相对简单的制造技术提供完全交错的电容器，同时仍然提供增加的电容。

公开(公告)号：US4685197A

公开(公告)日：1987-08-11

申请号：US781846

申请日：1986-01-07

申请人： Howard L. Tigelaar ,  Bert R. Riemenschneider

发明人： Howard L. Tigelaar ,  Bert R. Riemenschneider

IPC分类号： H01L21/02 ,  H01L21/8229 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L27/10 ,  G11C11/34 ,  H01L27/04

CPC分类号： H01L27/1085 ,  H01L21/8229 ,  H01L27/10805 ,  H01L28/40 ,  H01L29/945 ,  Y10T29/435

摘要： The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates. The area etched away is then filled with a suitable dielectric and a contact is made to the unetched interleaved plates. Thus a fully interleaved capacitor is provided using relatively simple fabrication techniques while still providing increased capacitance.

摘要翻译： 本发明提供了一种用于制造该结构的结构和方法，该结构在占用集成电路的最小表面积的同时提供了比现有技术更大的电容。 本发明通过交错多个电容器板来提供增加的电容，同时占据与现有技术的电容器相同的表面积，从而提供本发明提供的电容的一部分。 本发明通过提供一种电容器堆叠来制造，该电容器堆叠包括可被选择性蚀刻并由适当的介电材料分离的材料的交错板。 当一组交错板被蚀刻时，屏蔽该堆叠的一部分。 交错板的蚀刻部分由合适的电介质填充，并且与剩余的板接触。 然后将堆叠的不同部分暴露于蚀刻另一组交错板的蚀刻。 然后用合适的电介质填充被蚀刻的区域，并且对未蚀刻的交错板进行接触。 因此，使用相对简单的制造技术提供完全交错的电容器，同时仍然提供增加的电容。

公开(公告)号：US5625220A

公开(公告)日：1997-04-29

申请号：US287323

申请日：1994-08-08

申请人： David K.-Y. Liu ,  Kueing-Long Chen ,  Bert R. Riemenschneider

发明人： David K.-Y. Liu ,  Kueing-Long Chen ,  Bert R. Riemenschneider

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： This antifuse includes: a sublithographic conductive pattern (18); an antifuse material (24) overlying said sublithographic conductive pattern (18); and a conductive layer (26) overlying the antifuse material (24) to form a reduced area antifuse (10). Other devices, systems and methods are also disclosed.

摘要翻译： 该反熔丝包括：亚光刻导电图案（18）; 覆盖所述亚光刻导电图案（18）的反熔丝材料（24）; 以及覆盖所述反熔丝材料（24）以形成减少区域反熔丝（10）的导电层（26）。 还公开了其他装置，系统和方法。

公开(公告)号：US4924437A

公开(公告)日：1990-05-08

申请号：US130774

申请日：1987-12-09

申请人： James L. Paterson ,  David D. Wilmoth ,  Bert R. Riemenschneider

发明人： James L. Paterson ,  David D. Wilmoth ,  Bert R. Riemenschneider

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L27/115 ,  H01L29/7883

摘要： An EEPROM cell and array of cells is disclosed having buried diffusion source/drain lines and buried diffusion erase lines. The cells further include coupling between the floating gate and control gate above the source/drain diffusion. The disclosed cell allows high packing density and operation at low voltages.

公开(公告)号：US5595922A

公开(公告)日：1997-01-21

申请号：US330655

申请日：1994-10-28

申请人： Howard L. Tigelaar ,  Bert R. Riemenschneider ,  Richard A. Chapman ,  Andrew T. Appel

发明人： Howard L. Tigelaar ,  Bert R. Riemenschneider ,  Richard A. Chapman ,  Andrew T. Appel

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/823857 ,  H01L21/28167 ,  H01L21/28211 ,  Y10S438/911 ,  Y10S438/981

摘要： One embodiment of the present invention is a method of simultaneously forming high-voltage (12) and low-voltage (10) devices on a single substrate (14), the method comprising: forming a thin oxide layer (18) on the substrate, the thin oxide layer having a desired thickness for a gate oxide for the low-voltage device; selectively forming a gate structure (30) for the high-voltage device, the thin oxide is situated between the gate structure and the substrate; and selectively thickening the thin oxide under the gate structure while keeping the thin oxide layer utilized for the low-voltage device at the desired thickness.

摘要翻译： 本发明的一个实施例是在单个衬底（14）上同时形成高电压（12）和低电压（10）器件的方法，所述方法包括：在衬底上形成薄的氧化物层（18） 所述薄氧化物层具有用于所述低压器件的栅极氧化物的期望厚度; 选择性地形成用于高电压器件的栅极结构（30），薄氧化物位于栅极结构和衬底之间; 并且在栅极结构下选择性地增厚薄氧化物，同时将用于低电压器件的薄氧化物层保持在期望的厚度。