公开(公告)号：US20070252282A1

公开(公告)日：2007-11-01

申请号：US11772899

申请日：2007-07-03

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through, the dielectric layer; forming a sacrificial layer on opposing sidewalls of the trench; filling the trench with a electrical conductor; and removing a portion of the sacrificial layer from between the electrical conductor and the dielectric layer to form air-gaps.

摘要翻译： 气隙绝缘互连结构及其制造方法，包括：在基板上形成电介质层; 在所述电介质层的顶表面上形成覆盖层; 通过所述覆盖层形成沟槽，所述沟槽朝向所述衬底延伸并且穿过所述电介质层; 在沟槽的相对侧壁上形成牺牲层; 用电导体填充沟槽; 以及从所述电导体和所述电介质层之间移除所述牺牲层的一部分以形成气隙。

公开(公告)号：US20070235818A1

公开(公告)日：2007-10-11

申请号：US11277677

申请日：2006-03-28

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78687

摘要： Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.

摘要翻译： 本文的实施方案提供了用于双平面互补金属氧化物半导体的器件，方法等。 该器件包括在体硅衬底上的鳍式晶体管。 鳍型晶体管包括外鳍区域和中心半导体鳍片区域，其中中心鳍片区域具有{110}晶体取向沟道表面。 外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。 诱发杂质的应变接触体硅衬底，其中应变诱导杂质包括锗和/或碳。 此外，鳍型晶体管在其顶面包括厚氧化物构件。 翅片型晶体管还包括在第一晶体取向表面上的第一晶体管，其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。

公开(公告)号：US20070212857A1

公开(公告)日：2007-09-13

申请号：US11749417

申请日：2007-05-16

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/20

CPC分类号： H01L27/1207 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.

摘要翻译： 具有在SOI区域和体区域中制造的器件的集成电路，其中所述区域通过填充有外延沉积材料的沟槽连接。 填充的沟槽提供连接SOI和块区域的连续的半导体表面。 SOI和体区可以具有相同或不同的晶体取向。 本集成电路通过形成具有由嵌入式侧壁间隔物（由电介质制成）隔开的SOI和主体区域的衬底制成。 蚀刻侧壁间隔物，形成随后用外延材料填充的沟槽。 在平坦化之后，衬底具有SOI和具有连续半导体表面的体区。 对接的P-N结和硅化物层可以在SOI和体区之间提供电连接。

公开(公告)号：US20070023756A1

公开(公告)日：2007-02-01

申请号：US11161213

申请日：2005-07-27

申请人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak ,  BethAnn Rainey

发明人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak ,  BethAnn Rainey

IPC分类号： H01L29/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

摘要： A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.

摘要翻译： 场效应晶体管（FET）和形成FET的方法包括：衬底; 衬底上的硅锗（SiGe）层; 在SiGe层上并邻近SiGe层的半导体层; 与衬底相邻的绝缘层，SiGe层和半导体层; 邻近绝缘层的一对第一栅极结构; 以及绝缘层上的第二栅极结构。 优选地，绝缘层与SiGe层的侧表面，半导体层的上表面，半导体层的下表面和半导体层的侧表面相邻。 优选地，SiGe层包含碳。 优选地，该对第一栅极结构基本上横向于第二栅极结构。 此外，该对第一栅极结构优选地被绝缘层封装。

公开(公告)号：US20060273438A1

公开(公告)日：2006-12-07

申请号：US11145423

申请日：2005-06-03

申请人： Brent Anderson ,  Edmund Sprogis

发明人： Brent Anderson ,  Edmund Sprogis

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/585 ,  H01L23/576 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention is directed to an integrated circuit module device. The device includes a first semiconductor chip having a first circuit layer and at least one first interconnection element disposed on a first chip surface. The at least one first interconnection element is electrically coupled to the first circuit layer. A second semiconductor chip includes a second circuit layer and at least one second interconnection element disposed on a second chip surface. The at least one second interconnection element is electrically coupled to the second circuit layer. The at least one first interconnection element is connected to the at least one second interconnection element to establish electrical continuity between the first circuit layer and the second circuit layer. The first surface is adjoined to the second surface. At least one ring delay circuit includes a first ring delay path partially disposed on the first circuit layer and a second ring delay path partially disposed on the second circuit layer. The first ring delay path and the second ring delay path form a signal path having a predetermined measurement signature. The ring delay circuit compares the predetermined measurement signature to a test measurement signature.

公开(公告)号：US20060234456A1

公开(公告)日：2006-10-19

申请号：US11426623

申请日：2006-06-27

申请人： Brent Anderson ,  William Clark ,  Edward Nowak

发明人： Brent Anderson ,  William Clark ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/7887 ,  Y10S438/954

摘要： A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.

摘要翻译： 四位FinFET存储单元，制造四位FinFET存储单元的方法和由四位FINFET存储单元形成的NVRAM。 该四位存储单元包括在FinFET的鳍的第一侧壁上的电介质层的相对端中的两个电荷存储区，以及位于鳍的翅片的第二侧壁上的电介质层的相对端中的两个附加电荷存储区 FinFET，第一和第二侧壁彼此相对。

公开(公告)号：US20060199465A1

公开(公告)日：2006-09-07

申请号：US11072921

申请日：2005-03-03

申请人： Brent Anderson

发明人： Brent Anderson

IPC分类号： A63H3/06 ,  A63H5/00

CPC分类号： A63H27/10 ,  A63H2027/1008 ,  A63H2027/1058 ,  A63H2027/1091

摘要： The present invention provides a balloon weight system for an inflatable balloon having, singularly or in any combination, an electronic music producing device, a line distance adjusting device, to produce a descending and/or ascending of the balloon, and a fragrance distribution device.

摘要翻译： 本发明提供了一种用于充气气球的球囊重量系统，其具有单独地或以任何组合形成电子音乐产生装置，线距离调节装置，以产生气球的下降和/或上升，以及香料分配装置。

公开(公告)号：US20060176418A1

公开(公告)日：2006-08-10

申请号：US11347125

申请日：2006-02-03

申请人： Brent Anderson ,  Aaron Friedman ,  James Watson ,  Neal Hofmann ,  Richard Meissner

发明人： Brent Anderson ,  Aaron Friedman ,  James Watson ,  Neal Hofmann ,  Richard Meissner

IPC分类号： G02F1/1333

CPC分类号： G06F3/041 ,  G06F1/1607 ,  G06F3/0428

摘要： A method and apparatus for mounting a sensor module adjacent the edge of a display including a housing wherein the housing forms at least a first mounting surface, the apparatus including a first coupler, a first adhesive layer securing the first coupler to the first mounting surface and a second coupler linked to the sensor module and coupled to the first coupler wherein the second coupler is adjustable to modify the relative position of the sensor module to the display unit.

摘要翻译： 一种用于将传感器模块安装在包括壳体的显示器的边缘附近的方法和装置，其中壳体形成至少第一安装表面，该装置包括第一耦合器，将第一耦合器固定到第一安装表面的第一粘合剂层， 链接到传感器模块并耦合到第一耦合器的第二耦合器，其中第二耦合器是可调节的，以修改传感器模块与显示单元的相对位置。

公开(公告)号：US20060131339A1

公开(公告)日：2006-06-22

申请号：US11020380

申请日：2004-12-22

申请人： Brent Anderson

发明人： Brent Anderson

IPC分类号： B65D37/00

CPC分类号： B65D81/2038

摘要： The present invention provides a one way valve having a valve body, a wall, a fluid inlet, and a fluid outlet. The valve has a plunger which is moveable with respect to the valve body from a first position to a second position. The valve also has a diaphragm positioned in the valve body for movement between a third position and a fourth position when the plunger is in the first position. When the diaphragm is in the third position the fluid outlet is closed and when the diaphragm is in the fourth position the fluid outlet is open.

摘要翻译： 本发明提供一种具有阀体，壁，流体入口和流体出口的单向阀。 该阀具有可从第一位置到第二位置相对于阀体移动的柱塞。 阀还具有位于阀体中的隔膜，用于当柱塞处于第一位置时在第三位置和第四位置之间移动。 当隔膜处于第三位置时，流体出口关闭，当隔膜处于第四位置时，流体出口打开。

公开(公告)号：US20060097329A1

公开(公告)日：2006-05-11

申请号：US10904357

申请日：2004-11-05

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L27/1203 ,  H01L29/66795

摘要： A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.

摘要翻译： 翅片型场效应晶体管（FinFET）具有鳍状物，其具有中心沟道部分，端部包括源极和漏极区域以及从鳍片的沟道部分的侧壁延伸的沟道延伸部。 该结构还包括覆盖沟道部分和沟道延伸部的栅极绝缘体以及栅极绝缘体上的栅极导体。 通道扩展增加了鳍片的通道部分的电容。