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公开(公告)号：US20070023756A1
公开(公告)日：2007-02-01
申请号：US11161213
申请日：2005-07-27
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/78615 , H01L29/78687
摘要： A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.
摘要翻译： 场效应晶体管（FET）和形成FET的方法包括：衬底; 衬底上的硅锗（SiGe）层; 在SiGe层上并邻近SiGe层的半导体层; 与衬底相邻的绝缘层，SiGe层和半导体层; 邻近绝缘层的一对第一栅极结构; 以及绝缘层上的第二栅极结构。 优选地，绝缘层与SiGe层的侧表面，半导体层的上表面，半导体层的下表面和半导体层的侧表面相邻。 优选地，SiGe层包含碳。 优选地，该对第一栅极结构基本上横向于第二栅极结构。 此外，该对第一栅极结构优选地被绝缘层封装。
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公开(公告)号：US20060286724A1
公开(公告)日：2006-12-21
申请号：US11160361
申请日：2005-06-21
申请人： Brent Anderson , Matthew Breitwisch , Edward Nowak
发明人： Brent Anderson , Matthew Breitwisch , Edward Nowak
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.
摘要翻译： 公开了具有背栅的三栅场效应晶体管和形成晶体管的相关方法。 具体地说，后门结合在翅片的下部。 三栅结构形成在翅片上并与后门电隔离。 背栅可用于控制FET的阈值电压。 在一个实施例中，背栅极延伸到p型硅衬底中的n阱。 与n阱的接触允许将电压施加到后门。 在n阱和p衬底之间产生的二极管将流过n阱的电流与衬底上的其他器件隔离，使得后栅极可以被独立地偏置。 在另一个实施例中，背栅极延伸到p型硅衬底上的绝缘体层上的n型多晶硅层。 与n型多晶硅层的接触允许电压施加到后门。 通过多晶硅层延伸到绝缘体层的沟槽隔离结构将流过多晶硅层的电流与硅衬底上的其它器件隔离。
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3.发明申请公开(公告)号：US20060068531A1
公开(公告)日：2006-03-30
申请号：US10539335
申请日：2002-12-19
申请人： Matthew Breitwisch , Edward Nowak
发明人： Matthew Breitwisch , Edward Nowak
IPC分类号： H01L21/84 , H01L21/00 , H01L21/8238
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , H01L29/66787 , H01L29/785
摘要： An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118), and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.
摘要翻译： 诸如SRAM单元（130）的集成电路，包括反向的FinFET晶体管（P 2）和FinFET晶体管（N 3）。 反向FinFET晶体管包括由衬底上的半导体结构（100）形成的第一栅极区（108），由半导体层（104）组成的第一体区，其具有设置在第一栅极区上的第一沟道区（112） 以及形成在第一通道区域的任一侧上的源极（110）和漏极（114）。 FinFET晶体管（N 3）耦合到反向的FinFET晶体管，并且包括由半导体结构（102）形成的具有第二沟道区（118）的第二体区，以及源极（116）和漏极（120） 形成在所述第二沟道区的任一侧上，以及由所述半导体层构成的第二栅极区（122），设置在所述第二沟道区上。
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公开(公告)号：US07906368B2
公开(公告)日：2011-03-15
申请号：US11771501
申请日：2007-06-29
IPC分类号： H01L21/06
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.
摘要翻译： 本发明的实施例包括形成非易失性相变存储器（PCM）单元的方法。 该方法包括形成至少一个底部电极; 在所述底部电极的上表面的至少一部分上形成至少一个相变材料层; 在所述相变材料层的上表面的至少一部分上形成至少一个加热层; 并且将加热器层成形为锥形，使得加热器层的上表面的横截面宽度大于与相变材料层接触的加热器层的底表面的横截面宽度。
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公开(公告)号：US20090289242A1
公开(公告)日：2009-11-26
申请号：US12511602
申请日：2009-07-29
IPC分类号： H01L47/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element. The element includes at least one bottom electrode; at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; and at least one heater layer on at least a portion of an upper surface of the phase change material layer, wherein the heater layer has a tapered shape such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.
摘要翻译： 本发明的实施例包括形成非易失性相变存储器（PCM）单元的方法。 该方法包括形成至少一个底部电极; 在所述底部电极的上表面的至少一部分上形成至少一个相变材料层; 在所述相变材料层的上表面的至少一部分上形成至少一个加热层; 并且将加热器层成形为锥形，使得加热器层的上表面的横截面宽度大于与相变材料层接触的加热器层的底表面的横截面宽度。 本发明的另一实施例包括可配置为用作非易失性存储元件的相变存储器（PCM）结构。 该元件包括至少一个底部电极; 在所述底部电极的上表面的至少一部分上的至少一个相变材料层; 以及在所述相变材料层的上表面的至少一部分上的至少一个加热层，其中所述加热器层具有锥形形状，使得所述加热器层的上表面的横截面宽度比 加热器层的底表面的与相变材料层接触的横截面宽度。
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公开(公告)号：US20070201267A1
公开(公告)日：2007-08-30
申请号：US11361811
申请日：2006-02-24
IPC分类号： G11C11/00
CPC分类号： G11C7/062 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2211/5634
摘要： A memory includes a phase-change memory cell and a circuit. The phase-change memory cell can be set to at least three different states including a substantially crystalline state, a substantially amorphous state, and at least one partially crystalline and partially amorphous state. The circuit applies a first voltage across the memory cell to determine whether the memory cell is set at the substantially crystalline state and applies a second voltage across the memory cell to determine whether the memory cell is set at a partially crystalline and partially amorphous state.
摘要翻译： 存储器包括相变存储器单元和电路。 相变存储单元可以被设置为至少三种不同的状态，包括基本上为结晶状态，基本为非晶状态，以及至少一种部分结晶和部分非晶状态。 电路在存储器单元两端施加第一电压以确定存储器单元是否被设置在基本上为结晶状态，并且在该存储单元上施加第二电压以确定存储器单元是否被设置为部分结晶和部分非晶态。
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公开(公告)号：US20090001341A1
公开(公告)日：2009-01-01
申请号：US11771501
申请日：2007-06-29
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element. The element includes at least one bottom electrode; at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; and at least one heater layer on at least a portion of an upper surface of the phase change material layer, wherein the heater layer has a tapered shape such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.
摘要翻译： 本发明的实施例包括形成非易失性相变存储器（PCM）单元的方法。 该方法包括形成至少一个底部电极; 在所述底部电极的上表面的至少一部分上形成至少一个相变材料层; 在所述相变材料层的上表面的至少一部分上形成至少一个加热层; 并且将加热器层成形为锥形，使得加热器层的上表面的横截面宽度大于与相变材料层接触的加热器层的底表面的横截面宽度。 本发明的另一实施例包括可配置为用作非易失性存储元件的相变存储器（PCM）结构。 该元件包括至少一个底部电极; 在所述底部电极的上表面的至少一部分上的至少一个相变材料层; 以及在所述相变材料层的上表面的至少一部分上的至少一个加热层，其中所述加热器层具有锥形形状，使得所述加热器层的上表面的横截面宽度比 加热器层的底表面的与相变材料层接触的横截面宽度。
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公开(公告)号：US20070246748A1
公开(公告)日：2007-10-25
申请号：US11410466
申请日：2006-04-25
IPC分类号： H01L29/768
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1625 , H01L45/1666
摘要： A memory cell comprises a dielectric layer and a phase change material. The dielectric layer defines a trench having both a wide portion and a narrow portion. The narrow portion is substantially narrower than the wide portion. The phase change material, in turn, at least partially fills the wide and narrow portions of the trench. What is more, the phase change material within the narrow portion of the trench defines a void. Data can be stored in the memory cell by heating the phase change material by applying a pulse of switching current to the memory cell. Advantageously, embodiments of the invention provide high switching current density and heating efficiency so that the magnitude of the switching current pulse can be reduced.
摘要翻译： 存储单元包括介电层和相变材料。 电介质层限定了具有宽部分和窄部分的沟槽。 狭窄部分基本上比宽部分窄。 相变材料又至少部分地填充沟槽的宽而窄的部分。 此外，沟槽狭窄部分内的相变材料限定了空隙。 通过向存储单元施加切换电流的脉冲来加热相变材料，可以将数据存储在存储单元中。 有利地，本发明的实施例提供高开关电流密度和加热效率，从而可以减小开关电流脉冲的幅度。
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9.发明授权Reprogrammable integrated circuit (IC) with overwritable nonvolatile storage 失效具有可重写非易失性存储的可重复编程集成电路（IC）公开(公告)号：US07123517B2
公开(公告)日：2006-10-17
申请号：US10711819
申请日：2004-10-07
申请人： Matthew Breitwisch , Chung H. Lam , Steven Mittl , Jian W. Zhu
发明人： Matthew Breitwisch , Chung H. Lam , Steven Mittl , Jian W. Zhu
摘要： A reprogrammable integrated circuit (IC) including overwritable nonvolatile storage cells. Cell contents are compared in a differential sense amplifier against a variable reference signal that has a number of selectable reference levels corresponding to reprogrammed cell threshold voltages. With each write cycle the nonvolatile storage cells are overwritten and then, compared against a different, e.g., higher, selectable reference level.
摘要翻译： 包括可重写非易失性存储单元的可重复编程集成电路（IC）。 在差分读出放大器中将单元内容与可变参考信号进行比较，该可变参考信号具有对应于重新编程的单元阈值电压的多个可选参考电平。 在每个写入周期中，非易失性存储单元被覆盖，然后与不同的，例如更高的可选参考电平进行比较。
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10.发明授权公开(公告)号：US07378710B2
公开(公告)日：2008-05-27
申请号：US10539335
申请日：2002-12-19
IPC分类号： H01L21/00
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , H01L29/66787 , H01L29/785
摘要： An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118), and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.
摘要翻译： 诸如SRAM单元（130）的集成电路，包括反向的FinFET晶体管（P 2）和FinFET晶体管（N 3）。 反向FinFET晶体管包括由衬底上的半导体结构（100）形成的第一栅极区（108），由半导体层（104）组成的第一体区，其具有设置在第一栅极区上的第一沟道区（112） 以及形成在第一通道区域的任一侧上的源极（110）和漏极（114）。 FinFET晶体管（N 3）耦合到反向的FinFET晶体管，并且包括由半导体结构（102）形成的具有第二沟道区（118）的第二体区，以及源极（116）和漏极（120） 形成在所述第二沟道区的任一侧上，以及由所述半导体层构成的第二栅极区（122），设置在所述第二沟道区上。
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