公开(公告)号：US20150069490A1

公开(公告)日：2015-03-12

申请号：US14022646

申请日：2013-09-10

申请人： Jane A. Yater ,  Cheong Min Hong ,  Sung-Taeg Kang

发明人： Jane A. Yater ,  Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11568 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.

公开(公告)号：US09252246B2

公开(公告)日：2016-02-02

申请号：US13972372

申请日：2013-08-21

申请人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

发明人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42332

摘要： A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

摘要翻译： 制造半导体结构的方法包括在NVM区域中形成选择栅极和电荷存储层。 通过沉积保形层，接着进行回蚀而形成控制栅极。 图案化的蚀刻导致将电荷存储层的一部分留在选择栅极上并在控制栅极之下并且从逻辑区域去除电荷存储层。 形成在逻辑区域中的逻辑门结构具有被绝缘层包围的金属功函数。

公开(公告)号：US08048738B1

公开(公告)日：2011-11-01

申请号：US12760313

申请日：2010-04-14

申请人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

发明人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/461

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.

摘要翻译： 一种形成半导体器件的方法包括在衬底上形成电介质层。 该方法还包括在电介质层上形成选择栅极层。 该方法还包括以第一蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第一部分，其中以第一蚀刻速率蚀刻选择栅极层的步骤包括使用氧化剂至少氧化 在介质层下面的衬底的顶部以形成氧化物层。 该方法还包括以低于第一蚀刻速率的第二蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第二部分，其中以第二蚀刻速率蚀刻选择栅极层的步骤包括仅去除 电介质层的顶部。

公开(公告)号：US20110256705A1

公开(公告)日：2011-10-20

申请号：US12760313

申请日：2010-04-14

申请人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

发明人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.

摘要翻译： 一种形成半导体器件的方法包括在衬底上形成电介质层。 该方法还包括在电介质层上形成选择栅极层。 该方法还包括以第一蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第一部分，其中以第一蚀刻速率蚀刻选择栅极层的步骤包括使用氧化剂至少氧化 在介质层下面的衬底的顶部以形成氧化物层。 该方法还包括以低于第一蚀刻速率的第二蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第二部分，其中以第二蚀刻速率蚀刻选择栅极层的步骤包括仅去除 电介质层的顶部。

公开(公告)号：US08877585B1

公开(公告)日：2014-11-04

申请号：US13969180

申请日：2013-08-16

申请人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang

发明人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/11546 ,  H01L29/42332 ,  H01L29/66825

摘要： A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.

摘要翻译： 使用具有非易失性存储器（NVM）部分，第一高压部分，第二高压部分和逻辑部分的衬底制造半导体结构的方法包括在主要的氧化物层上形成第一导电层 NVM部分中的衬底表面，第一和第二高压部分以及逻辑部分。 在NVM部分中制造存储单元，同时第一导电层保留在第一和第二高压部分和逻辑部分中。 图案化第一导电层以在第一和第二高压部分中形成晶体管栅极。 在NVM部分和第一和第二高压部分上形成保护掩模。 晶体管栅极形成在逻辑部分中，同时保护掩模保留在NVM部分以及第一和第二高电压部分中。

公开(公告)号：US20140209995A1

公开(公告)日：2014-07-31

申请号：US13753047

申请日：2013-01-29

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： Non-volatile memory (NVM) cells having carbon impurities are disclosed along with related manufacturing methods. The carbon impurities can be introduced using a variety of techniques, including through epitaxial growth of silicon-carbon (SiC) layers and/or carbon implants. Further, the carbon impurities can be introduced into one or more structures within NVM cells, including source regions, drain regions, gate regions, and/or charge storage layers. For discrete charge storage layers that utilize nanocrystal structures, carbon impurities can be introduced into the nanocrystal charge storage layers. The disclosed embodiments are useful for a variety of NVM cell types including split-gate NVM cells, floating gate NVM cells, discrete charge storage NVM cells, and/or other desired NVM cells. Advantageously, the carbon impurities introduce tensile stress into the cell structures, and this tensile stress helps maintain NVM system performance and data retention even as device geometries are reduced.

摘要翻译： 公开了具有碳杂质的非易失性存储器（NVM）单元以及相关的制造方法。 可以使用各种技术引入碳杂质，包括通过硅 - 碳（SiC）层和/或碳植入物的外延生长。 此外，可以将碳杂质引入NVM单元内的一个或多个结构，包括源极区，漏极区，栅极区和/或电荷存储层。 对于利用纳米晶体结构的离散电荷存储层，可将碳杂质引入纳米晶电荷存储层。 所公开的实施例对于包括分裂门NVM单元，浮动栅极NVM单元，分立电荷存储NVM单元和/或其它期望的NVM单元的各种NVM单元类型是有用的。 有利地，碳杂质将细胞结构中的拉伸应力引入，并且即使在减小器件几何形状的情况下，该拉伸应力有助于维持NVM系统性能和数据保持。

公开(公告)号：US08163609B2

公开(公告)日：2012-04-24

申请号：US12964727

申请日：2010-12-09

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02601 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.

摘要翻译： 使用半导体衬底制造半导体器件的方法包括在半导体衬底上形成具有第一带能的第一绝缘层。 具有第二带能的第一半导体层形成在第一绝缘层上。 第一半导体层被退火以从第一半导体层形成多个第一电荷保持器球。 在多个第一电荷保持器球的每个电荷保持器球上形成第一保护膜。 在多个第一电荷保持器球上形成具有第三带能的第二半导体层。 第二半导体层被退火以在多个第一电荷保持器球上从第二半导体层形成多个存储小球。 第二带能量的大小在第一带能量的大小和第三带能量的大小之间。

公开(公告)号：US20150054050A1

公开(公告)日：2015-02-26

申请号：US13972372

申请日：2013-08-21

申请人： ASANGA H. PERERA ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Janes A. Yater

发明人： ASANGA H. PERERA ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Janes A. Yater

IPC分类号： H01L27/115 ,  H01L29/66

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42332

摘要： A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

摘要翻译： 制造半导体结构的方法包括在NVM区域中形成选择栅极和电荷存储层。 通过沉积保形层，接着进行回蚀而形成控制栅极。 图案化的蚀刻导致将电荷存储层的一部分留在选择栅极上并在控制栅极之下并且从逻辑区域去除电荷存储层。 形成在逻辑区域中的逻辑门结构具有被绝缘层包围的金属功函数。

公开(公告)号：US08953378B2

公开(公告)日：2015-02-10

申请号：US13536307

申请日：2012-06-28

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/3459

摘要： A method for programming a split gate memory cell includes performing a first programming of the split gate memory cell in a first programming cycle of the split gate memory cell; and, subsequent to the performing the first programming of the split gate memory cell, performing a second programming of the split gate memory cell in the first programming cycle, wherein the first programming is characterized as one of source-side injection (SSI) programming and channel-initiated secondary electron (CHISEL) programming, and the second programming is characterized as the other of SSI programming and CHISEL programming.

摘要翻译： 用于对分割门存储器单元进行编程的方法包括在分离栅极存储单元的第一编程周期中执行分离栅极存储单元的第一编程; 并且在执行所述分离栅极存储器单元的第一编程之后，在所述第一编程周期中执行所述分离栅极存储单元的第二编程，其中所述第一编程被表征为源侧注入（SSI）编程之一， 通道启动的二次电子（CHISEL）编程，第二个编程被表征为SSI编程和CHISEL编程中的另一个。

公开(公告)号：US20150001606A1

公开(公告)日：2015-01-01

申请号：US13929924

申请日：2013-06-28

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L29/49 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28518 ,  H01L27/105 ,  H01L27/11536 ,  H01L29/42332 ,  H01L29/45 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7882

摘要： A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

摘要翻译： 使用衬底形成分离栅极存储单元结构的方法包括形成包括选择栅极和覆盖在选择栅极上的电介质部分的栅极堆叠。 电荷存储层形成在包括在栅叠层上的衬底上。 导电材料的第一侧壁间隔物沿着延伸经过选择栅极的顶部的栅极堆叠的第一侧壁形成。 电介质材料的第二侧壁间隔物沿着第一侧壁间隔件上的第一侧壁形成。 使用第二侧壁间隔物作为掩模使第一侧壁间隔物的一部分硅化，由此硅化物不延伸到电荷存储层。