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    METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG)
    14.
    发明申请
    METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG) 有权
    包括高介电常数门绝缘子和金属栅的晶体管中的工作功能工程的方法和结构（HKMG）

    公开(公告)号：US20110248350A1

    公开(公告)日：2011-10-13

    申请号：US12757323

    申请日：2010-04-09

    申请人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

    发明人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

    IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L29/78

    CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/6659

    摘要： Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

    摘要翻译： 实现了包括包括Hi-K栅极电介质和金属栅极的栅极结构的场效应晶体管的开关阈值的调整，并且通过在与导电沟道相邻的薄界面层中提供固定的电荷材料来在NFET和PFET之间协调切换阈值 根据设计将Hi-K材料，优选氧化铪或HfSiON粘附到半导体材料上而不是将固定的电荷材料扩散到Hi-K材料中之后施加的晶体管。 固定电荷材料与晶体管的导通通道的接近程度增加了由于金属栅极的功函数而导致的固定电荷材料的调整阈值的有效性，特别是当相同的金属或合金用于NFET和PFET时 在集成电路中; 防止阈值正确协调。

    HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION
    15.
    发明申请
    HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION 有权
    具有隔离区域的最小重叠的高K电介质和金属栅极堆叠

    公开(公告)号：US20110227171A1

    公开(公告)日：2011-09-22

    申请号：US13150378

    申请日：2011-06-01

    申请人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey Sleight

    发明人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey Sleight

    IPC分类号： H01L29/51

    CPC分类号： H01L29/517 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

    摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

    摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

    HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION AND RELATED METHODS
    16.
    发明申请
    HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION AND RELATED METHODS 失效
    具有隔离区域的最小重叠的高K电介质和金属栅极堆栈及相关方法

    公开(公告)号：US20090152650A1

    公开(公告)日：2009-06-18

    申请号：US11954775

    申请日：2007-12-12

    申请人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey W Sleight

    发明人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey W Sleight

    IPC分类号： H01L29/49 ,  H01L21/283

    CPC分类号： H01L29/517 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

    摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

    摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

    High-K dielectric and metal gate stack with minimal overlap with isolation region
    18.
    发明授权
    High-K dielectric and metal gate stack with minimal overlap with isolation region 有权
    高K电介质和金属栅极堆叠与隔离区域重叠

    公开(公告)号：US08232606B2

    公开(公告)日：2012-07-31

    申请号：US13150378

    申请日：2011-06-01

    申请人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey Sleight

    发明人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey Sleight

    IPC分类号： H01L29/76

    CPC分类号： H01L29/517 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

    摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

    摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

    High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods
    19.
    发明授权
    High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods 失效
    高k介质和金属栅极堆叠与隔离区域和相关方法的重叠最小

    公开(公告)号：US08021939B2

    公开(公告)日：2011-09-20

    申请号：US11954775

    申请日：2007-12-12

    申请人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey W Sleight

    发明人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey W Sleight

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/517 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

    摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

    摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

    Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG)
    20.
    发明授权
    Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG) 有权
    晶体管中工作功能工程的方法和结构包括高介电常数栅极绝缘体和金属栅极（HKMG）

    公开(公告)号：US08728925B2

    公开(公告)日：2014-05-20

    申请号：US13463283

    申请日：2012-05-03

    申请人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

    发明人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/6659

    摘要： Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

    摘要翻译： 实现了包括包括Hi-K栅极电介质和金属栅极的栅极结构的场效应晶体管的开关阈值的调整，并且通过在与导电沟道相邻的薄界面层中提供固定的电荷材料来在NFET和PFET之间协调切换阈值 根据设计将Hi-K材料，优选氧化铪或HfSiON粘附到半导体材料上而不是将固定的电荷材料扩散到Hi-K材料中之后施加的晶体管。 固定电荷材料与晶体管的导通通道的接近程度增加了由于金属栅极的功函数而导致的固定电荷材料的调整阈值的有效性，特别是当相同的金属或合金用于NFET和PFET时 在集成电路中; 防止阈值正确协调。