公开(公告)号：US5276862A

公开(公告)日：1994-01-04

申请号：US682801

申请日：1991-04-09

申请人： Lowell D. McCulley ,  Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards

发明人： Lowell D. McCulley ,  Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards

IPC分类号： G06F11/14 ,  G06F11/16 ,  G06F11/00

CPC分类号： G06F11/1441 ,  G06F11/1641 ,  G06F11/1637

摘要： In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.

摘要翻译： 为了收集，存储和交付（如果需要的话）中央处理器保险箱信息，采用多相时钟来捕获（一个完整的时钟周期）保存存储信息，这些信息通常包括所有（或选定的）数据操作中的所有软件可见寄存器 通过临时存储（在多相时钟的影响下）将缓存存储信息路由到高速缓存数据阵列中并进入特殊目的XRAM模块，从而使CPU的芯片。 因此，在检测到故障时，XRAM中有效的保险箱信息可用于分析，如果适用，在刚刚发生故障的连续点恢复运行。

公开(公告)号：US5263034A

公开(公告)日：1993-11-16

申请号：US594880

申请日：1990-10-09

申请人： Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards ,  Bruce E. Flocken

发明人： Russell W. Guenthner ,  Clinton B. Eckard ,  Leonard Rabins ,  William A. Shelly ,  Ronald E. Lange ,  David S. Edwards ,  Bruce E. Flocken

IPC分类号： G06F11/16

CPC分类号： G06F11/1641

摘要： In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.

摘要翻译： 为了在包括AX（地址和执行）模块，DN（十进制数字）模块和FP（浮点））模块的中央处理器的基本处理单元（BPU）中提供有效的错误检测，每个模块在 主/从对，并且将每个对中执行的数据操作操作的本地结果进行比较，以便在结果被验证以供后续在中央处理器中使用之前进行身份验证。

公开(公告)号：US4521851A

公开(公告)日：1985-06-04

申请号：US434122

申请日：1982-10-13

申请人： Leonard G. Trubisky ,  William A. Shelly

发明人： Leonard G. Trubisky ,  William A. Shelly

IPC分类号： G06F9/28 ,  G06F9/34 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3889 ,  G06F12/0848 ,  G06F9/34 ,  G06F9/3844 ,  G06F9/3863 ,  G06F9/3885

摘要： A central processor for a general-purpose digital data processing system. The processor has a pair of caches, an operand cache for operands and an instruction cache for instructions, as well as a plurality of execution units, where each execution unit executes a different set of instructions of the instruction repertoire of the central processor. An instruction fetch unit fetches instructions from the instruction cache and stores them in an instruction stack. The central pipeline unit which has five stages obtains instructions of a given program in program order from the instruction stack of the instruction fetch unit. In the first stage of the central pipeline unit, the instruction is decoded; in the second, the address preparation of an operand whose address is included in the instruction is initiated; in the third cycle, the address preparation is completed and the operand cache is accessed; in the fourth cycle, the operand is selected from the operand cache; and, in the fifth cycle, the instruction and operand are transmitted to the one of the plurality of execution units capable of executing the instruction. The results of the execution of each instruction by each execution unit are stored in a results stack associated therewith. A collector unit causes the results of the execution of the instructions of the program in execution to be stored in a master safe store register in program order, which is determined by the order of issuance of the instructions by the central pipeline unit. The collector also issues write commands to store results of the execution of instructions into the operand cache.

摘要翻译： 用于通用数字数据处理系统的中央处理器。 处理器具有一对高速缓存，用于操作数的操作数高速缓存和用于指令的指令高速缓存，以及多个执行单元，其中每个执行单元执行中央处理器的指令集的不同指令集。 指令提取单元从指令高速缓存中取出指令并将它们存储在指令栈中。 具有五个阶段的中央流水线单元从指令提取单元的指令堆栈获得给定程序的指令。 在中央流水线单元的第一阶段，指令被解码; 在第二个地址中，启动地址包含在指令中的操作数的地址准备; 在第三周期中，地址准备完成并且操作数缓存被访问; 在第四个周期中，从操作数缓存中选择操作数; 并且在第五周期中，指令和操作数被发送到能够执行指令的多个执行单元中的一个。 每个执行单元执行每个指令的结果被存储在与其相关联的结果堆栈中。 收集器单元使得执行中的程序的指令的执行结果以程序顺序存储在主安全存储寄存器中，该程序顺序由中央流水线单元发出指令的顺序确定。 收集器还发出写入命令以将执行指令的结果存储到操作数缓存中。

公开(公告)号：US4471432A

公开(公告)日：1984-09-11

申请号：US434196

申请日：1982-10-13

申请人： John E. Wilhite ,  William A. Shelly ,  Russell W. Guenthner ,  Leonard G. Trubisky ,  Joseph C. Circello

发明人： John E. Wilhite ,  William A. Shelly ,  Russell W. Guenthner ,  Leonard G. Trubisky ,  Joseph C. Circello

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3867

摘要： A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system. Instructions containing address information and an instruction field are obtained in program order from an instruction fetch unit of the CPU. In a first stage, requiring one clock period, the address information of an instruction is utilized to form the carrys and sums of an effective address and to initiate the formation of a virtual address. Concurrently, the instruction field is decoded to produce memory command signals and data alignment signals. In a second stage, the formation of the effective and virtual addresses initiated in the first stage is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU. Also during the second stage, memory command signals are sent to the cache unit and the instruction field is converted to an execution code for one of a plurality of execution units, and the execution unit to execute the code is designated. In a third stage, the virtual address is converted to a physical address, or real page number, which is transmitted to the cache unit. The execution code is sent to the designated execution unit; however, if the execution unit is the central unit, the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. In the fourth stage, data alignment control signals are sent to a distributor of the central execution pipeline unit.

摘要翻译： 一种用于启动通用数字数据处理系统的同步中央处理器单元（CPU）的指令执行的方法和中央执行流水线单元。 从CPU的指令提取单元以程序顺序获取包含地址信息和指令字段的指令。 在需要一个时钟周期的第一阶段中，使用指令的地址信息来形成有效地址的进位和和并且启动虚拟地址的形成。 同时，指令字段被解码以产生存储器命令信号和数据对准信号。 在第二阶段中，完成在第一阶段中发起的有效和虚拟地址的形成，虚拟地址的字地址部分被发送到CPU的高速缓存单元。 此外，在第二阶段期间，存储器命令信号被发送到高速缓存单元，并且指令字段被转换为多个执行单元之一的执行代码，并且指定执行代码执行代码。 在第三阶段中，将虚拟地址转换为物理地址或实际页号，该地址被发送到高速缓存单元。 执行代码被发送到指定的执行单元; 然而，如果执行单元是中央单元，则执行单元是中央单元，该单元的执行代码被转换为执行单元控制信号。 在第四阶段，将数据对准控制信号发送到中央执行流水线单元的分配器。

公开(公告)号：US4006466A

公开(公告)日：1977-02-01

申请号：US562364

申请日：1975-03-26

申请人： Garvin Wesley Patterson ,  William A. Shelly ,  Jaime Calle ,  Earnest M. Monahan

发明人： Garvin Wesley Patterson ,  William A. Shelly ,  Jaime Calle ,  Earnest M. Monahan

IPC分类号： G06F13/12 ,  G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F1/00

CPC分类号： G06F9/4812 ,  G06F13/26 ,  G06F9/4818 ,  G06F9/4831

摘要： An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations. Each multiplexer unit includes a plurality of storage registers which are operatively coupled to the programmable interface associated therewith for receiving control information therefrom designating the priority to be given by the unit to the processing of different types of interrupt signals received from devices associated therewith in addition to information designating which one of a set of processing routines to be used in servicing the interrupt.

摘要翻译： 输入/输出数据处理系统包括多个有源模块，多个无源模块和至少一个存储器模块和具有多个端口的系统接口单元，每个端口连接到不同的模块之一。 每个模块通过多个不同的接口连接到一个端口。 有源模块包括用于处理中断和执行命令序列的输入/输出处理单元和用于直接控制存储器模块与耦合到多路复用器单元的多个端口中的不同端口的任何外围设备之间的传输的多路复用器单元。 系统的不同模块包括用于将命令信息传送到多路复用器单元的可编程接口和与其相关联的设备，以使不同类型的控制与输入/输出数据传送操作并行进行。 每个多路复用器单元包括多个存储寄存器，其可操作地耦合到与其相关联的可编程接口，用于接收控制信息，从而指定由该单元给予的优先级，以处理从与其相关联的设备接收的不同类型的中断信号， 指定用于维护中断的一组处理例程中的哪一个的信息。

公开(公告)号：US06970977B2

公开(公告)日：2005-11-29

申请号：US10403703

申请日：2003-03-31

申请人： Wayne R. Buzby ,  Charles P. Ryan ,  Robert J. Baryla ,  William A. Shelly ,  Lowell D. McCulley

发明人： Wayne R. Buzby ,  Charles P. Ryan ,  Robert J. Baryla ,  William A. Shelly ,  Lowell D. McCulley

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/084

摘要： In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.

摘要翻译： 一种多处理器写入高速缓存数据处理系统，包括：存储器; 至少第一和第二共享高速缓存; 耦合存储器和共享缓存的系统总线; 至少一个处理器具有分别耦合到每个共享高速缓存的专用高速缓存; 方法和装置，用于防止存储在存储器中的门字的所有权，其控制对在处理器中运行的进程共享的共同代码/数据的访问，通过该处理器，由给定处理器通过执行连续的交换操作来获得门字的读取副本 内存和给定处理器的共享缓存，以及给定的处理器的共享缓存和专用缓存。 如果门字被发现是OPEN，则由给定的处理器关闭，并且在给定处理器的专用高速缓存和共享高速缓存之间执行连续的交换操作，并且共享高速缓存和存储器将门字CLOSEd写入存储器，使得给定的处理器获得 独占访问受管制的通用代码/数据。 当给定的处理器完成使用通用代码/数据时，它将门字OPEN写入其专用缓存，并且在给定处理器的专用高速缓存和共享高速缓存之间执行连续的交换操作，共享高速缓存和存储器将门槛OPEN写入存储器 。

公开(公告)号：US06898738B2

公开(公告)日：2005-05-24

申请号：US09907302

申请日：2001-07-17

申请人： Charles P. Ryan ,  William A. Shelly ,  Stephen A. Schuerich

发明人： Charles P. Ryan ,  William A. Shelly ,  Stephen A. Schuerich

IPC分类号： G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F11/00

CPC分类号： G06F11/1666 ,  G06F11/167 ,  G06F11/20 ,  G06F12/0802

摘要： Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to the search value. At the same time, they are also parity checked and compared against each other. If a match is made on either the primary entry or the duplicate entry, and that entry does not have a parity error, a cache “hit” is indicated. All single bit cache tag parity errors are detected and compensated for. Almost all multiple bit cache tag parity errors are detected.

摘要翻译： 通过复制缓存标签条目，缓存内存，从而提高计算机系统的可靠性。 每个缓存标签都有一个主条目和一个重复条目。 然后，当关联搜索缓存标签时，将主条目和重复条目都与搜索值进行比较。 同时，他们也是平等检查和相互比较。 如果在主条目或重复条目上进行匹配，并且该条目没有奇偶校验错误，则指示缓存“命中”。 检测和补偿所有单位缓存标签奇偶校验错误。 检测到几乎所有多个位缓存标签奇偶校验错误。

公开(公告)号：US06530076B1

公开(公告)日：2003-03-04

申请号：US09472114

申请日：1999-12-23

申请人： Charles P. Ryan ,  Ron Yoder ,  William A. Shelly

发明人： Charles P. Ryan ,  Ron Yoder ,  William A. Shelly

IPC分类号： G06F944

CPC分类号： G06F11/3636 ,  G06F9/30185 ,  G06F11/28 ,  G06F11/3466

摘要： A processor (92) contains a Trace RAM (210) for tracing internal processor signals and operands. A first trace mode separately traces microcode instruction execution and cache controller execution. Selectable groups of signals are traced from both the cache controller (256) and the arithmetic (AX) processor (260). A second trace mode selectively traces full operand words that result from microcode instruction (242). Each microcode instruction word (242) has a trace enable bit (244) that when enabled causes the results of that microcode instruction (242) to be recorded in the Trace RAM (210).

摘要翻译： 处理器（92）包含用于跟踪内部处理器信号和操作数的跟踪RAM（210）。 第一个跟踪模式分别跟踪微代码指令执行和高速缓存控制器执行。 高速缓存控制器（256）和算术（AX）处理器（260）都可追踪可选组的信号。 第二跟踪模式选择性地跟踪由微代码指令（242）产生的全部操作数字。 每个微代码指令字（242）具有跟踪使能位（244），当使能时，使得该微代码指令（242）的结果被记录在跟踪RAM（210）中。

公开(公告)号：US5963973A

公开(公告)日：1999-10-05

申请号：US796309

申请日：1997-02-07

申请人： Elisabeth Vanhove ,  Minoru Inoshita ,  William A. Shelly ,  Robert J. Baryla

发明人： Elisabeth Vanhove ,  Minoru Inoshita ,  William A. Shelly ,  Robert J. Baryla

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0833

摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for storing identification words identifying information blocks resident in the cache memory and including a status field indicative of the write permission authority the local CPU has on the block, an output buffer for storing the identification words of a block resident in the cache memory for which the CPU does not have and seeks write permission and for selectively sending identification words and an invalidate command onto the CPU bus, an input buffer for storing the identification words of all recent write permission requests in the group, a comparator for comparing the identification words in the output buffer with the identifications in the input buffer and control logic, responsive to the comparator sensing a compare condition (typically indicating a request by another CPU for write permission on the same block for which the local CPU has also requested write permission), for aborting the write permission request of the local CPU and establishing a retry process.

摘要翻译： 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓冲存储器和高速缓存控制器，其具有：处理器目录，用于存储标识驻留在高速缓冲存储器中的信息块的识别字，并且包括指示本地CPU在块上的写许可权限的状态字段;输出缓冲器 用于存储驻留在CPU不具有的高速缓冲存储器中的块的识别字，并且寻求写许可，并且用于选择性地将标识字和无效命令发送到CPU总线上;输入缓冲器，用于存储所有最近的识别字 响应于比较器感测比较条件（通常指示另一个CPU对另一个CPU的写入许可的请求），比较器用于将输出缓冲器中的识别字与输入缓冲器和控制逻辑中的标识进行比较 相同的块，本地CPU也要求写入许可），用于aborti 纳入本地CPU的写许可请求并建立重试过程。

公开(公告)号：US5644761A

公开(公告)日：1997-07-01

申请号：US893871

申请日：1992-06-05

申请人： Ronald W. Yoder ,  Ronald E. Lange ,  William A. Shelly ,  Russell W. Guenthner ,  Richard L. Demers

发明人： Ronald W. Yoder ,  Ronald E. Lange ,  William A. Shelly ,  Russell W. Guenthner ,  Richard L. Demers

IPC分类号： G06F9/26 ,  G06F9/22

CPC分类号： G06F9/267

摘要： In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.

摘要翻译： 为了有效地执行在中央处理单元中执行扩展指令所需的微步骤，提供了具有其自己的定序器的主序列控制器和单独的基本操作控制器以及半自主运行的能力。 通常，主序列控制器确定基本操作控制器的操作，但是在执行例如需要扩展基本操作的多字指令的情况下，基本操作控制器暂时控制主控制器，直到 扩展基本操作已经完成。 结果是相对简单的定序器，其支持紧密的微编码功能，其中许多顺序决定可以被预先确定。