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    METHOD FOR MAKING A QUANTUM DEVICE
    12.
    发明公开
    METHOD FOR MAKING A QUANTUM DEVICE 审中-公开

    公开(公告)号：US20230186136A1

    公开(公告)日：2023-06-15

    申请号：US18057435

    申请日：2022-11-21

    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

    Inventor： Cyrille LE ROYER ,  François LEFLOCH ,  Fabrice NEMOUCHI ,  Nicolas POSSEME

    IPC: G06N10/40 ,  H10N60/12

    CPC classification number: G06N10/40 ,  H10N60/12

    Abstract: A method for producing a quantum device comprising forming a supraconductive layer, forming a mask on the supraconductive layer, the mask comprising masking patterns and at least two openings alternately in a direction, the at least two openings being separated from one another by a separation distance pi (i=1 . . . n), and further each having a width di (i=1 . . . n+1), such as the separation distance pi and a width di are less than a coherence length of a Cooper pair in said supraconductive material, and modifying, through the at least two openings, of the exposed portions of the supraconductive layer, so as to form at least two barriers of width di separating the supraconductive regions.

    METHOD OF MAKING AN INDIVIDUALIZATION ZONE OF AN INTEGRATED CIRCUIT
    15.
    发明申请
    METHOD OF MAKING AN INDIVIDUALIZATION ZONE OF AN INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220028803A1

    公开(公告)日：2022-01-27

    申请号：US17443138

    申请日：2021-07-21

    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

    Inventor： Nicolas POSSEME ,  Stefan LANDIS

    IPC: H01L23/00 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522

    Abstract: The invention relates to a method for making an individualization zone of a microchip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a level of interconnections (30A) comprising vias (30), the method comprising the following steps: providing the first level (10A) and a dielectric layer (200, 201, 202), making a hard metal mask (300) on the dielectric layer (200, 201, 202), etching the dielectric layer (200, 201, 202) through the mask openings (301) by etching based on fluorinated chemistry, preferably oxidizing the hard metal mask (300) by hydrolysis so as to form randomly distributed residues (31) at certain openings (320R), filling the openings (320, 320R) so as to form at least the vias (30) of the level of interconnections (30A), said vias (30) comprising functional vias (30OK) at the openings without residues (320) and inactive vias (30KO) at the openings with residues (320R).

    METHOD FOR ETCHING A THREE-DIMENSIONAL DIELECTRIC LAYER
    16.
    发明申请
    METHOD FOR ETCHING A THREE-DIMENSIONAL DIELECTRIC LAYER 审中-公开

    公开(公告)号：US20200251570A1

    公开(公告)日：2020-08-06

    申请号：US16722390

    申请日：2019-12-20

    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

    Inventor： Nicolas POSSEME ,  Vincent Ah-Leung ,  Olivier Pollet

    IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

    Abstract: There is provided a method for etching a dielectric layer covering at least partially a flank of a structure made of a semi-conductive material, the structure having at least one face, the method including a plurality of sequences, each including at least the following steps: a main oxidation so as to form an oxide film; a main anisotropic etching of the oxide film, carried out so as to etch a portion of the oxide film extending parallel to the flanks and at least some of the dielectric layer, be stopped before etching the structure and a whole thickness of another portion of the oxide film extending perpendicularly to the flanks, the steps being repeated until the complete removal of the dielectric layer located on the flanks of the structure.

    METHOD OF ETCHING A DIELECTRIC LAYER
    17.
    发明申请
    METHOD OF ETCHING A DIELECTRIC LAYER 审中-公开

    公开(公告)号：US20200227271A1

    公开(公告)日：2020-07-16

    申请号：US16722228

    申请日：2019-12-20

    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

    Inventor： Nicolas POSSEME ,  Frederic LE ROUX

    IPC: H01L21/311 ,  H01L21/3115

    Abstract: A method is provided for etching a dielectric layer disposed on at least one layer based on gallium nitride (GaN), the dielectric layer being formed by a material based on one from SixNy and SixOy, the method including: first etching of the dielectric layer on only part of a thickness to define therein a partial opening and a residual portion situated in line with the opening and having another thickness; implanting ions in line with the opening over a thickness greater than the another thickness to modify a material of the dielectric layer over an entire thickness of the residual portion, and modify a material of the base layer of GaN; removing the residual portion by a second etching, selective of the modified dielectric layer with respect to the nonmodified material and with respect to the modified layer based on GaN; and annealing of the layer based on GaN.

    METHOD FOR FORMING SPACERS FOR A TRANSISTOR GATE
    18.
    发明申请
    METHOD FOR FORMING SPACERS FOR A TRANSISTOR GATE 有权
    用于形成晶体闸门的间隔物的方法

    公开(公告)号：US20160372331A1

    公开(公告)日：2016-12-22

    申请号：US15185281

    申请日：2016-06-17

    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

    Inventor： Nicolas POSSEME

    IPC: H01L21/28 ,  H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/31155 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795

    Abstract: A method for forming spacers of a gate of a transistor is provided, including forming a protective layer covering the gate; after the forming the protective layer, at least one step of forming a carbon film on the transistor; removing portions of the carbon film located on a top and on either side of the gate; modifying the protective layer on the top of the gate and on either side of the gate; and removing the modified protective layer.

    Abstract translation: 提供一种用于形成晶体管的栅极的间隔物的方法，包括形成覆盖栅极的保护层; 在形成保护层之后，在晶体管上形成碳膜的至少一个步骤; 去除位于门的顶部和两侧的碳膜的部分; 改变栅极顶部和栅极两侧的保护层; 并除去改性保护层。

    METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR
    19.
    发明申请
    METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR 审中-公开
    形成晶体管栅极的方法

    公开(公告)号：US20160020152A1

    公开(公告)日：2016-01-21

    申请号：US14797345

    申请日：2015-07-13

    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

    Inventor： Nicolas POSSEME

    IPC: H01L21/8238 ,  H01L29/51 ,  H01L21/265 ,  H01L29/16 ,  H01L29/66 ,  H01L21/31 ,  H01L21/311

    CPC classification number: H01L21/823864 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/823468 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/16 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

    Abstract: A method for forming spacers of a field effect transistor gate, comprising forming a nitride layer covering the gate, modifying the nitride layer by contacting the nitride layer with plasma comprising ions heavier than hydrogen and CxHy so as to form a nitride-based modified layer and a carbon film; with the modifying being so executed that plasma creates an anisotropic bombardment with hydrogen (H)-based ions from CxHy in a favorite direction parallel to flanks of the gate and so as to modify an upper portion of the thickness of the nitride-based layer at the level of the flanks of the gate only, with the anisotropic bombardment with ions heavier than hydrogen enabling the carbon in CxHy to form a carbon film, and removing the nitride-based modified layer, using etching of the nitride-based modified layer to said carbon film and to the non-modified portions which the spacers are made of.

    Abstract translation: 一种用于形成场效应晶体管栅极的间隔物的方法，包括形成覆盖栅极的氮化物层，通过使氮化物层与包含比氢和CxHy重的离子的等离子体接触来改变氮化物层，以形成氮化物基改性层， 碳膜; 修改如此执行，使得等离子体在与栅极的侧面平行的收敛方向上从CxHy以氢（H）为基础的离子产生各向异性轰击，并且修饰氮化物基层的厚度的上部， 栅极侧面的水平，各向异性轰击离子比氢重，使得CxHy中的碳能够形成碳膜，并且通过将氮化物基改性层蚀刻到所述氮化物基改性层，去除氮化物基改性层 碳膜和间隔物制成的非改性部分。

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