公开(公告)号：US10853550B1

公开(公告)日：2020-12-01

申请号：US16027231

申请日：2018-07-03

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Richard J. O'Donovan ,  Michael Tian

IPC: G06F30/367 ,  G06F17/50 ,  G06F111/10 ,  G06F119/18

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

公开(公告)号：US10699051B1

公开(公告)日：2020-06-30

申请号：US16024495

申请日：2018-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Regis Colwell ,  Hua Luo ,  Namita Rane ,  Elias L. Fallon

IPC: G06F30/392 ,  G06N5/04 ,  G06N20/00 ,  G06F111/04 ,  G06F111/20

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations. An improved approach to perform cross-validations is provided.

公开(公告)号：US10262092B1

公开(公告)日：2019-04-16

申请号：US15589762

申请日：2017-05-08

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Catherine Bunting

IPC: G06F17/50

Abstract: A method for determining mismatch variation of circuit components in a circuit is provided. The method includes determining a mismatch contribution for a specification of an integrated circuit design and displaying a list of components in the circuit design sorted according to the mismatch contribution. The method also includes displaying an adjustable scale for a size of the component, modifying the circuit design according to with the size of the component adjusted according to a user input to the adjustable scale, determining an adjusted mismatch contribution of the component, and displaying in the list of components a modified value of the mismatch contribution, and a modified value of an overall standard deviation for the specification in the circuit design.

公开(公告)号：US08954910B1

公开(公告)日：2015-02-10

申请号：US14166119

申请日：2014-01-28

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Wangyang Zhang

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5009 ,  G06F2217/10 ,  G06F2217/16

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. When the samples exceed the mismatch parameters, a linear model is solved by least squares. Otherwise, a linear model is solved by orthogonal matching pursuit (OMP), and if that solution is too inaccurate then a new mixed method builds a better linear model. If the linear solution is too inaccurate, a full linear and quadratic model is made using OMP to select the most important variables, and the full model is fitted using OMP with selected cross terms. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions.

Abstract translation: 一种用于计算设备失配变化对电路性能变化的贡献的系统，方法和计算机程序产品。 实施例估计了模拟电路设计中的哪些单独设备对电路性能的影响最大，同时比传统的多元线性回归要少得多的仿真。 当样本超过失配参数时，通过最小二乘求解线性模型。 否则，通过正交匹配追求（OMP）解决线性模型，如果该解决方案太不准确，则新的混合方法建立更好的线性模型。 如果线性解决方案太不准确，则使用OMP来选择最重要的变量来完成线性和二次模型，并且使用具有所选交叉项的OMP拟合完整模型。 这些实施例总结了每个设备中的输出差异，并且基于总结的贡献对不匹配贡献进行排序。

公开(公告)号：US08813009B1

公开(公告)日：2014-08-19

申请号：US13830696

申请日：2013-03-14

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Wangyang Zhang

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10 ,  G06F2217/16

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. An ordered metric allocates output variance contributions for each input mismatch parameter in a linear model. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions. Additional sensitivity analysis can derive a final accurate linear contribution. Embodiments can reduce required simulations by a factor of ten.

Abstract translation: 一种用于计算设备失配变化对电路性能变化的贡献的系统，方法和计算机程序产品。 实施例估计了模拟电路设计中的哪些单独设备对电路性能的影响最大，同时比传统的多元线性回归要少得多的仿真。 有序指标在线性模型中为每个输入失配参数分配输出方差贡献。 这些实施例总结了每个设备中的输出差异，并且基于总结的贡献对不匹配贡献进行排序。 额外的灵敏度分析可以得出最终的精确线性贡献。 实施例可以将所需的模拟量减少10倍。

公开(公告)号：US11087060B1

公开(公告)日：2021-08-10

申请号：US16524859

申请日：2019-07-29

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon ,  Regis R. Colwell ,  Hua Luo ,  Namita Bhushan Rane ,  Sheng Qian

IPC: G06F30/39 ,  G06N20/00

Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and training a model using at least one predictor associated with the electronic design layout. Embodiments may further include obtaining an updated model, based upon, at least in part, the training. Embodiments may also include applying the updated model to a second electronic design schematic or a second electronic design layout, wherein one or more hard constraints or one or more soft constraints or both are created, based upon, at least in part, the model.

公开(公告)号：US10949596B1

公开(公告)日：2021-03-16

申请号：US16742266

申请日：2020-01-14

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hua Luo ,  Regis R. Colwell ,  Qian Xu

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/31 ,  G06N3/12 ,  G06F7/22 ,  G06F111/02

Abstract: Embodiments may include receiving an unplaced layout associated with an electronic circuit design and one or more grouping requirements. Embodiments may further include identifying instances that need to be placed at the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may also analyzing one or more instances that need to be placed at the unplaced layout and the one or more areas of the unplaced layout configured to receive the one or more instances. Embodiments may further include determining a location and an orientation for each of the one or more instances based upon, at least in part, the analyzing. Embodiments may also include generating a placed layout based upon, at least in part, the determined location and orientation for each of the one or more instances. Embodiments may further include during the generation of the placed layout, routing the placed layout.

公开(公告)号：US10909293B1

公开(公告)日：2021-02-02

申请号：US16655570

申请日：2019-10-17

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Richard J. O'Donovan ,  Michael Tian

IPC: G06F30/367 ,  G06F119/18 ,  G06F111/10

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

公开(公告)号：US10776548B1

公开(公告)日：2020-09-15

申请号：US15471871

申请日：2017-03-28

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Wangyang Zhang

IPC: G06F30/367 ,  G06F111/10

Abstract: A method for determining the tail performance of an integrated circuit is described. The method includes simulating the integrated circuit over samples to obtain values for circuit specifications and sorting the circuit specifications based on an expected number of samples. The method also includes arranging a sequence of samples from the universe according to a sequence in the group of circuit specifications, simulating the integrated circuit with one of the sequence of samples to obtain at least one circuit specification, removing the at least one circuit specification from the group when it satisfies the stop criterion, and modifying a model for a second circuit specification based on the at least one circuit specification. The computer-implemented method also includes reordering the group of circuit specifications based on the model and determining an integrated circuit performance based on a simulation result for the at least one circuit specification.

公开(公告)号：US10747936B1

公开(公告)日：2020-08-18

申请号：US16527412

申请日：2019-07-31

Applicant: Cadence Design Systems, Inc.

Inventor： Hua Luo ,  Regis R. Colwell ,  Wangyang Zhang

IPC: G06F30/394 ,  G06N3/12

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a two stage routing analysis, wherein a first stage analysis is an intra-row routing analysis and a second stage is an inter-row routing analysis. Embodiments may also include generating an optimized routing of the one or more nets and displaying the optimized routing at a graphical user interface.