公开(公告)号：US4517226A

公开(公告)日：1985-05-14

申请号：US503255

申请日：1983-06-10

申请人： Livio Baldi ,  Aldo Maggis

发明人： Livio Baldi ,  Aldo Maggis

IPC分类号： H01L21/52 ,  B23K35/00 ,  H01L21/24 ,  H01L21/285 ,  H01L21/301 ,  H01L21/58 ,  B05D5/12

CPC分类号： B23K35/001 ,  H01L21/244 ,  H01L21/28512 ,  B23K2035/008

摘要： On the back of a wafer there are deposited firstly a gold layer and then an aluminium layer (eventually including a small silicon percent). It is finally carried out a thermic treatment at low temperature, which causes the aluminium migration towards the wafer through the gold layer.

摘要翻译： 在晶片的背面，首先沉积金层，然后沉积铝层（最终包括小的硅百分比）。 最终在低温下进行热处理，这导致铝通过金层向晶片迁移。

公开(公告)号：US06812531B1

公开(公告)日：2004-11-02

申请号：US09303055

申请日：1999-04-30

申请人： Livio Baldi ,  Paolo Ghezzi

发明人： Livio Baldi ,  Paolo Ghezzi

IPC分类号： H01L2976

CPC分类号： H01L27/11246 ,  H01L27/112

摘要： Matrix of memory cells formed using a method allowing for a self-alignment of the respective source region with the respective field oxide layer and the respective overlying polysilicon layer of each single cell of the matrix, the matrix including at least one first ROM memory cell suitable for permanently storing a first logic level, associated with a respective row and a respective column of the matrix, the first cell including a silicon substrate of a first conductivity type over which a first isolation region and a second isolation region are formed delimiting therebetween a longitudinal stripe, a gate element extending transversally through the stripe from at least one side of the first isolation region to at least one side of the second isolation region, a third region of a second conductivity type and a fourth region of a second conductivity type formed in the substrate along the stripe, and a field oxide region adapted to prevent the formation of a conductive channel in the substrate, and at least a second ROM cell for permanently storing a second logic level, identical to the first ROM memory cell but not provided with the field oxide region.

摘要翻译： 使用允许各个源区域与相应的场氧化物层和矩阵的每个单个单元的相应的上覆多晶硅层的自对准的方法形成的存储器单元的矩阵，该矩阵包括至少一个第一ROM存储器单元 用于永久存储与矩阵的相应行和相应列相关联的第一逻辑电平，第一单元包括第一导电类型的硅衬底，在其上形成第一隔离区域和第二隔离区域，第一隔离区域和第二隔离区域之间界定纵向 条形，从第一隔离区的至少一侧横穿条带延伸至第二隔离区的至少一侧的栅极元件，形成第二导电类型的第三区域和第二导电类型的第四区域 沿着条带的衬底，以及适于防止在子层中形成导电沟道的场氧化物区域 并且至少第二ROM单元用于永久地存储第二逻辑电平，与第一ROM存储器单元相同但不具有场氧化物区域。

公开(公告)号：US5850360A

公开(公告)日：1998-12-15

申请号：US607779

申请日：1996-02-27

申请人： Bruno Vajana ,  Livio Baldi

发明人： Bruno Vajana ,  Livio Baldi

IPC分类号： H01L21/8238 ,  H01L27/092 ,  G11C11/34

CPC分类号： H01L21/823878 ,  H01L27/0928

摘要： A CMOS device and process are disclosed in which two types of N-channel MOS transistors are provided, one being formed in a P-well and one being formed outside the P-well where the relatively low doping concentration of P-type substrate serves as a channel defining region. This second type N-channel transistor an support higher junction voltages due to the lower p-type doping concentration than is possible for the first type N-channel transistor formed in the higher doping concentration P-well. A mask is provided to prevent boron doping in the substrate at the site of the high voltage transistor during the implantation step which defines the P-well.

摘要翻译： 公开了一种CMOS器件和工艺，其中提供两种类型的N沟道MOS晶体管，一种形成在P阱中，一种形成在P阱外部，其中P型衬底的相对低的掺杂浓度用作 一个通道定义区域。 该第二类型N沟道晶体管由于较低掺杂浓度的P型掺杂浓度而支持较高的结电压，这对于在较高掺杂浓度P阱中形成的第一型N沟道晶体管是可能的。 提供掩模以在限定P阱的注入步骤期间防止在高压晶体管的位置处的衬底中的硼掺杂。

公开(公告)号：US5708451A

公开(公告)日：1998-01-13

申请号：US681099

申请日：1996-07-22

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： G09G3/22 ,  H01J31/12 ,  G09G3/36

CPC分类号： G09G3/22 ,  H01J31/127 ,  G09G2320/0285 ,  G09G2320/043

摘要： Nonuniformities of luminance characteristics in a field emission display (FED) are compensated pixel by pixel by storing a matrix of correction values, determined by testing, and by applying a corrected drive signal through the relative column drive stages. The individual pixel's correction factor that is applied to the corresponding video signal may be stored in digital or analog form in a nonvolatile memory array. Various embodiments are described including the use of a second updatable RAM array wherein pixel's correction factors are calculated and stored at every power-on to provide an opportunity of trimming-up the luminance of the display for compensating long term decline of luminance due to the phosphors ageing process.

摘要翻译： 通过存储通过测试确定的校正值的矩阵以及通过相对列驱动级施加校正的驱动信号，逐像素地补偿场发射显示（FED）中的亮度特性的不均匀性。 应用于相应视频信号的单个像素的校正因子可以以数字或模拟形式存储在非易失性存储器阵列中。 描述了各种实施例，其包括使用第二可更新RAM阵列，其中在每次上电时计算和存储像素的校正因子，以提供修整显示器亮度的机会，以补偿由于荧光体引起的长期亮度下降 老化过程。

公开(公告)号：US4968645A

公开(公告)日：1990-11-06

申请号：US289391

申请日：1988-12-15

申请人： Livio Baldi ,  Paolo G. Cappelletti ,  Franco Maggioni

发明人： Livio Baldi ,  Paolo G. Cappelletti ,  Franco Maggioni

IPC分类号： H01L27/092 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/52 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L27/0688 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/106 ,  Y10S148/136

摘要： A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer of polycrystalline silicon, a layer of a silicide of a refractory metal overlying said polycrystalline silicon layer, and regions of preset area and preset paths formed in the polycrystalline silicon layer and the silicide layer; the preset area regions and preset paths forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.

摘要翻译： MOS或CMOS型的单片集成电路包括多晶硅的中间层，覆盖所述多晶硅层的难熔金属的硅化物层，以及形成在多晶硅层中的预设区域和预设路径的区域，以及 硅化物层 预设区域和预置路径分别形成用于中间连接水平的高电阻率电阻和低电阻率互连线。

公开(公告)号：US06399442B1

公开(公告)日：2002-06-04

申请号：US09415021

申请日：1999-10-07

申请人： Livio Baldi ,  Alfonso Maurelli

发明人： Livio Baldi ,  Alfonso Maurelli

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

摘要： A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell. Between selectively etching the dielectric and depositing a second polysilicon layer, a first sub-step of removing the first gate oxide layer in the region for the logic transistor, and a second sub-step of growing a second oxide gate layer over the region, the second gate oxide layer having a different thickness than the first gate oxide layer.

摘要翻译： 一种制造具有至少一个非易失性浮动栅极存储单元和至少一个逻辑晶体管的集成半导体器件的方法。 该方法包括在硅衬底上生长第一栅极氧化层，在第一栅极氧化物层上沉积第一多晶硅层，选择性地蚀刻和去除第一多晶硅层，以便限定存储单元的浮置栅极，按顺序引入掺杂剂 为了获得存储单元的源极和漏极区域，沉积介电层，在将形成逻辑晶体管的区域中选择性地蚀刻和去除电介质层和第一多晶硅层，沉积第二多晶硅层，选择性地蚀刻和去除 第二多晶硅层，以便限定逻辑晶体管的栅极和存储器单元的控制栅极。 在选择性地蚀刻电介质并沉积第二多晶硅层之间，去除用于逻辑晶体管的区域中的第一栅极氧化物层的第一子步骤以及在该区域上生长第二氧化物栅极层的第二子步骤， 第二栅极氧化物层具有与第一栅极氧化物层不同的厚度。

公开(公告)号：US5659501A

公开(公告)日：1997-08-19

申请号：US639931

申请日：1996-04-26

申请人： Livio Baldi ,  Federico Pio

发明人： Livio Baldi ,  Federico Pio

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C16/30 ,  G11C16/12

摘要： A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

摘要翻译： 编程电压通过控制栅极线提供给非易失性存储单元的控制栅极。 电源电压耦合到电容器的第一板，参考电压耦合到电容器的第二板。 然后将电源电压与第一板分离，并且参考电压与第二板脱离。 接下来，参考电压耦合到第一板以在第二板上产生编程电压。

公开(公告)号：US5534448A

公开(公告)日：1996-07-09

申请号：US282408

申请日：1994-07-28

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,doping the polycrystalline layer uncovered by said first mask,--providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, andN+ implanting the active areas of the N-channel transistors.

摘要翻译： 一种用于在用于模拟应用的半导体集成电路中形成低阈值电压P沟道MOS晶体管的工艺，所述电路包括形成在多晶硅层中的高电阻率电阻器和具有有源区域的N沟道MOS晶体管，所述有源区域已经通过 P型阱包括以下步骤：在所述电阻器和要形成低阈值电压P沟道晶体管的半导体区域上提供第一掩模，掺杂由所述第一掩模未覆盖的多晶层， - 提供第二掩模 用于保护要形成所述低阈值电压P沟道晶体管的电阻器和半导体区域的掩模，以及N +注入N沟道晶体管的有源区。

公开(公告)号：US5528536A

公开(公告)日：1996-06-18

申请号：US344232

申请日：1994-11-23

申请人： Livio Baldi ,  Federico Pio

发明人： Livio Baldi ,  Federico Pio

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C16/12

摘要： A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

摘要翻译： 编程电压通过控制栅极线提供给非易失性存储单元的控制栅极。 电源电压耦合到电容器的第一板，参考电压耦合到电容器的第二板。 然后将电源电压与第一板分离，并且参考电压与第二板脱离。 接下来，参考电压耦合到第一板以在第二板上产生编程电压。

公开(公告)号：US5372956A

公开(公告)日：1994-12-13

申请号：US153620

申请日：1993-11-17

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/28525 ,  H01L23/485 ,  H01L2924/0002

摘要： Highly reliable direct contacts may be formed by defining a direct contact area within a larger area purposely implanted and diffused for ensuring electrical continuity in the semiconductor. Patterning may define the contacting polysilicon within an implanted direct contact area so that the definition edges thereof fall on a gate oxide layer thus preventing an etching of the semiconductor during the unavoidable over-etching that concludes the polysilicon patterning step. Preferably, a pre-definition of the direct contact area is performed through a first, deposited layer of polysilicon, which effectively protects a gate oxide layer during a HF wash prior to depositing a second, contacting layer of polysilicon of adequate thickness.

摘要翻译： 可以通过在有意植入和扩散的更大区域内限定直接接触区域来形成高度可靠的直接接触，以确保半导体中的电连续性。 图案化可以限定植入的直接接触区域内的接触多晶硅，使得其定义边缘落在栅极氧化物层上，从而防止了在不可避免的过蚀刻期间对半导体的蚀刻，从而得出结论多晶硅图案化步骤。 优选地，直接接触区域的预定义通过第一沉积多晶硅层进行，其在沉积足够厚度的多晶硅的第二接触层之前在HF洗涤期间有效地保护栅极氧化物层。