公开(公告)号：US20150287642A1

公开(公告)日：2015-10-08

申请号：US14245627

申请日：2014-04-04

申请人： International Business Machines Corporation

发明人： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L21/8249 ,  H01L21/02 ,  H01L21/24 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/735 ,  H01L29/66 ,  H01L21/285

CPC分类号： H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

摘要： In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

摘要翻译： 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 在晶片上形成虚拟栅极，其中伪栅极存在于作为双极晶体管的基极的晶片的一部分上。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 介电填料层沉积在围绕虚拟栅极的晶片上。 对绝缘填料层选择性地去除伪栅极，从而露出基底。 基座凹进。 碱从由SiGe，Ge和III-V材料组成的组中选择的外延材料再生长。 触点形成在基座上。 还提供了用于共同制造双极晶体管和CMOS FET器件的技术。

公开(公告)号：US4454528A

公开(公告)日：1984-06-12

申请号：US460556

申请日：1983-01-24

申请人： Richard K. Trueblood

发明人： Richard K. Trueblood

IPC分类号： H01L21/24 ,  H01L21/60 ,  H01L21/285

CPC分类号： H01L24/83 ,  H01L21/244 ,  H01L24/26 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351

摘要： To provide an electrically conductive p-type wafer backside for semiconductor integrated circuit chips (die), a process is provided consisting of applying a thin layer of aluminum on a silicon dioxide free surface of the chip, followed by a layer of gold, then alloying the metals to diffuse the gold and traces of aluminum into the chip surface. The surface thus prepared can then be advantageously die attachable to a receiving surface by either eutectic alloy or conductive polymer techniques.

摘要翻译： 为了提供用于半导体集成电路芯片（裸片）的导电p型晶片背面，提供了一种方法，该方法包括在芯片的无二氧化硅表面上施加薄的铝层，随后是一层金，然后合金化 金属将金和痕迹铝扩散到芯片表面。 因此，如此制备的表面可以有利地通过共晶合金或导电聚合物技术可附着到接收表面。

公开(公告)号：US4297391A

公开(公告)日：1981-10-27

申请号：US3945

申请日：1979-01-16

申请人： Joseph Lindmayer

发明人： Joseph Lindmayer

IPC分类号： H01L21/24 ,  H01L31/0224 ,  H01L31/04 ,  H01L21/283

CPC分类号： H01L21/244 ,  H01L31/022425 ,  Y02E10/50

摘要： A method of forming an electrical contact on the surface of a photovoltaic cell in which particles of electrically conductive material are formed at a temperature in excess of the alloying temperature of the material and silicon, and thereafter spraying, e.g., flame spraying, arc spraying, or plasma spraying, the particles to one or both major surfaces of the cell so that the particles alloy with the silicon and adhere to the surface of the cell.

摘要翻译： 在光伏电池的表面上形成电接触的方法，其中在超过材料和硅的合金化温度的温度下形成导电材料颗粒，然后喷涂，例如火焰喷涂，电弧喷涂， 或等离子体喷射，将颗粒施加到电池的一个或两个主表面，使得颗粒与硅合金并粘附到电池的表面。

公开(公告)号：US20170040219A1

公开(公告)日：2017-02-09

申请号：US15332207

申请日：2016-10-24

申请人： International Business Machines Corporation

发明人： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L21/8249 ,  H01L29/66 ,  H01L21/24 ,  H01L27/06 ,  H01L21/84 ,  H01L29/735 ,  H01L29/10

CPC分类号： H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

摘要： In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

摘要翻译： 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 在晶片上形成虚拟栅极，其中伪栅极存在于作为双极晶体管的基极的晶片的一部分上。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 介电填料层沉积在围绕虚拟栅极的晶片上。 对绝缘填料层选择性地去除伪栅极，从而露出基底。 基座凹进。 碱从由SiGe，Ge和III-V材料组成的组中选择的外延材料再生长。 触点形成在基座上。 还提供了用于共同制造双极晶体管和CMOS FET器件的技术。

公开(公告)号：US09401411B2

公开(公告)日：2016-07-26

申请号：US14802092

申请日：2015-07-17

申请人： FUJI ELECTRIC CO., LTD.

发明人： Fumikazu Imai

IPC分类号： H01L29/15 ,  H01L21/00 ,  H01L29/49 ,  H01L21/24 ,  H01L21/04 ,  H01L29/45 ,  H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/4975 ,  H01L21/0485 ,  H01L21/24 ,  H01L21/244 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/872

摘要： In some aspects of the invention, a layer containing titanium and nickel is formed on an SiC substrate. A nickel silicide layer containing titanium carbide can be formed by heating. A carbon layer precipitated is removed by reverse sputtering. Thus, separation of an electrode of a metal layer formed on nickel silicide in a subsequent step is suppressed. The effect of preventing the separation can be further improved when the relation between the amount of precipitated carbon and the amount of carbon in titanium carbide in the surface of nickel silicide from which the carbon layer has not yet been removed satisfies a predetermined condition.

公开(公告)号：US09373696B2

公开(公告)日：2016-06-21

申请号：US14617314

申请日：2015-02-09

申请人： GLOBALFOUNDRIES INC.

发明人： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet S. Ozcan ,  Zhen Zhang

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02 ,  H01L21/24 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/161

CPC分类号： H01L29/665 ,  H01L21/02381 ,  H01L21/02631 ,  H01L21/244 ,  H01L21/28518 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/161

摘要： In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.

公开(公告)号：US20150287650A1

公开(公告)日：2015-10-08

申请号：US14245683

申请日：2014-04-04

申请人： International Business Machines Corporation

发明人： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L21/84 ,  H01L21/02 ,  H01L21/24 ,  H01L27/12 ,  H01L21/225 ,  H01L29/66 ,  H01L29/735 ,  H01L21/3065 ,  H01L21/324

CPC分类号： H01L21/845 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0257 ,  H01L21/02595 ,  H01L21/225 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/244 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/06 ,  H01L29/0673 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/6625 ,  H01L29/6631 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/735 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/78696

摘要： In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. Fin hardmasks are formed on the wafer. A dummy gate is formed on the wafer, over the fin hardmasks. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer and the dummy gate is removed selective to the dielectric filler layer so as to form a trench in the filler layer. Fins are patterned in the wafer using the fin hardmasks exposed within the trench, wherein the fins will serve as a base region of the bipolar transistor device. The fins are recessed in the base region. The base region is re-grown from an epitaxial SiGe, Ge or III-V semiconductor material. A contact is formed to the base region.

摘要翻译： 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 翅片硬掩模形成在晶片上。 在晶片上，在翅片硬掩模上形成虚拟栅极。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 将介电填料层沉积在晶片上，并且将虚拟栅极选择性地去除介电填料层，以便在填料层中形成沟槽。 使用暴露在沟槽内的散热片硬掩模，在晶片中图案化鳍片，其中鳍片将用作双极晶体管器件的基极区域。 翅片凹入基部区域。 从外延SiGe，Ge或III-V半导体材料再生长基极区。 在基部区域形成接触。

公开(公告)号：US4293587A

公开(公告)日：1981-10-06

申请号：US959344

申请日：1978-11-09

申请人： Richard K. Trueblood

发明人： Richard K. Trueblood

IPC分类号： H01L21/24 ,  H01L21/60 ,  H01L21/285

CPC分类号： H01L24/83 ,  H01L21/244 ,  H01L24/26 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  Y10S148/02 ,  Y10S148/033 ,  Y10S438/906 ,  Y10S438/974

摘要： To provide an electrically conductive p-type wafer backside for semiconductor integrated circuit chips (die), a process is provided consisting of applying a thin layer of aluminum on a silicon dioxide free surface of the chip, followed by a layer of gold, then alloying the metals to diffuse the gold and traces of aluminum into the chip surface. The surface thus prepared can then be advantageously die attachable to a receiving surface by either eutectic alloy or conductive polymer techniques.

摘要翻译： 为了提供用于半导体集成电路芯片（裸片）的导电p型晶片背面，提供了一种方法，该方法包括在芯片的无二氧化硅表面上施加薄的铝层，随后是一层金，然后合金化 金属将金和痕迹铝扩散到芯片表面。 因此，如此制备的表面可以有利地通过共晶合金或导电聚合物技术可附着到接收表面。

公开(公告)号：US20180061956A1

公开(公告)日：2018-03-01

申请号：US15254302

申请日：2016-09-01

申请人： International Business Machines Corporation

发明人： Praneet ADUSUMILLI ,  Hemanth JAGANNATHAN ,  Christian LAVOIE

IPC分类号： H01L29/45 ,  H01L21/3215 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/223 ,  H01L21/24 ,  H01L27/092 ,  H01L29/167

CPC分类号： H01L29/45 ,  H01L21/2236 ,  H01L21/244 ,  H01L21/265 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/167 ,  H01L29/78

摘要： Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.

公开(公告)号：US20170062577A1

公开(公告)日：2017-03-02

申请号：US15351977

申请日：2016-11-15

申请人： MICRON TECHNOLOGY, INC.

发明人： Rhett T. Brewer ,  Durai V. Ramaswamy

IPC分类号： H01L29/423 ,  G11C14/00 ,  G11C16/04 ,  G11C16/08 ,  H01L29/788 ,  H01L27/115

CPC分类号： H01L29/42324 ,  G11C14/0018 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  H01L21/244 ,  H01L21/265 ,  H01L21/28273 ,  H01L21/44 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881

摘要： Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic to control access of the array of memory cells, wherein the array of memory cells includes a memory cell having a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, and wherein the charge storage structure includes a charge-storage material and a gettering agent.

摘要翻译： 具有与处理器通信的处理器和存储器件的设备，所述存储器设备包括存储器单元阵列和控制存储器单元阵列的访问的控制逻辑，其中所述存储器单元阵列包括具有第一 邻近半导体的介质，控制栅极，控制栅极和第一电介质之间的第二电介质，以及第一电介质和第二电介质之间的电荷存储结构，其中电荷存储结构包括电荷存储材料和吸气 代理商