公开(公告)号：US06188121B1

公开(公告)日：2001-02-13

申请号：US09119115

申请日：1998-07-20

申请人： Livio Baldi ,  Paolo Ghezzi ,  Alfonso Maurelli

发明人： Livio Baldi ,  Paolo Ghezzi ,  Alfonso Maurelli

IPC分类号： H01L2900

CPC分类号： H01L28/60 ,  H01L27/0805 ,  H01L29/94

摘要： A high voltage capacitor, integratable monolithically on a semiconductor substrate which accommodates a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer, comprises two elementary capacitors having a first common conductive plate which is formed in the first layer of polycrystalline silicon. Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.

摘要翻译： 一个高电压电容器，整体地集成在半导体衬底上，该半导体衬底上容纳由第二层多晶硅隔绝的第一多晶硅层覆盖的场氧化物区域，该第二层由多晶硅电介质层隔开，包括两个基本电容器，其具有第一公共导电板， 形成在第一层多晶硅中。 这些基本电容器中的每一个具有形成在第一板上方的第二多晶硅层中的第二导电板，并且包括作为两个板之间的隔离电介质的所述互聚电介质层。

公开(公告)号：US06812531B1

公开(公告)日：2004-11-02

申请号：US09303055

申请日：1999-04-30

申请人： Livio Baldi ,  Paolo Ghezzi

发明人： Livio Baldi ,  Paolo Ghezzi

IPC分类号： H01L2976

CPC分类号： H01L27/11246 ,  H01L27/112

摘要： Matrix of memory cells formed using a method allowing for a self-alignment of the respective source region with the respective field oxide layer and the respective overlying polysilicon layer of each single cell of the matrix, the matrix including at least one first ROM memory cell suitable for permanently storing a first logic level, associated with a respective row and a respective column of the matrix, the first cell including a silicon substrate of a first conductivity type over which a first isolation region and a second isolation region are formed delimiting therebetween a longitudinal stripe, a gate element extending transversally through the stripe from at least one side of the first isolation region to at least one side of the second isolation region, a third region of a second conductivity type and a fourth region of a second conductivity type formed in the substrate along the stripe, and a field oxide region adapted to prevent the formation of a conductive channel in the substrate, and at least a second ROM cell for permanently storing a second logic level, identical to the first ROM memory cell but not provided with the field oxide region.

摘要翻译： 使用允许各个源区域与相应的场氧化物层和矩阵的每个单个单元的相应的上覆多晶硅层的自对准的方法形成的存储器单元的矩阵，该矩阵包括至少一个第一ROM存储器单元 用于永久存储与矩阵的相应行和相应列相关联的第一逻辑电平，第一单元包括第一导电类型的硅衬底，在其上形成第一隔离区域和第二隔离区域，第一隔离区域和第二隔离区域之间界定纵向 条形，从第一隔离区的至少一侧横穿条带延伸至第二隔离区的至少一侧的栅极元件，形成第二导电类型的第三区域和第二导电类型的第四区域 沿着条带的衬底，以及适于防止在子层中形成导电沟道的场氧化物区域 并且至少第二ROM单元用于永久地存储第二逻辑电平，与第一ROM存储器单元相同但不具有场氧化物区域。

公开(公告)号：US5527728A

公开(公告)日：1996-06-18

申请号：US329309

申请日：1994-10-26

申请人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

发明人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7883 ,  H01L27/115 ,  Y10S438/911 ,  Y10S438/981

摘要： A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

摘要翻译： 一种用于在电可擦除和可编程只读存储器单元中形成薄氧化物部分的方法，包括使用增强的氧化效应和重掺杂的横向扩散，以获得其尺寸小于光刻方法的分辨率的隧道部分 用过的。

公开(公告)号：US5553017A

公开(公告)日：1996-09-03

申请号：US310836

申请日：1994-09-22

申请人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

发明人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

摘要翻译： 一种用于制造具有单个多晶硅级别的电可擦除和可编程只读存储器单元的方法，包括使用氧化硅牺牲层在有源区上产生高厚度氧化硅层。 为了提高可靠性，保护电池的有源区域免受重的源极和漏极注入。

公开(公告)号：US5194157A

公开(公告)日：1993-03-16

申请号：US884879

申请日：1992-05-18

申请人： Paolo Ghezzi ,  Renzo Gervasio

发明人： Paolo Ghezzi ,  Renzo Gervasio

IPC分类号： A61M1/34 ,  A61M1/36

CPC分类号： A61M1/3413 ,  A61M1/3417 ,  A61M1/3486 ,  A61M1/3472 ,  A61M1/3679 ,  Y10S210/929

摘要： Blood to be purified is passed through a haemofiltration element and a haemodialysis element in cascade and the ultrafiltrate output from the haemofiltration element is passed through a filter such as an activated carbon filter, preferably with uncoated activated carbon. The ultrafiltrate thus purified can then be used as a reinfusion solution to be readministered to the patient.

摘要翻译： 待纯化的血液级联通过血液透析元件和血液透析元件，并且来自血液滤过元件的超滤液输出通过过滤器，例如活性炭过滤器，优选未涂覆的活性炭。 因此，如此纯化的超滤液可用作再次输注溶液以再次给予患者。

公开(公告)号：US5132239A

公开(公告)日：1992-07-21

申请号：US574677

申请日：1990-08-30

申请人： Paolo Ghezzi ,  Carlo Riva ,  Grazia Valentini

发明人： Paolo Ghezzi ,  Carlo Riva ,  Grazia Valentini

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L21/31662 ,  H01L27/115 ,  H01L29/7883 ,  H01L21/28167 ,  H01L21/28211

摘要： The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor, sensing transistor having a floating gate, control gate with a capacitive coupling to the floating gate and a tunnel area with thin oxide, comprises a first step involving the definition of active areas free of field oxide, a second step involving an ionic implantation at a coupling area between the control gate and the floating gate, a third step involving the creation of gate oxide at the active areas, a fourth step involving an additional ionic implantation at said coupling area between the control gate and the floating gate and at said tunnel area, a fifth step involving the removal of the gate oxide superimposed over said areas, a sixth step involving the differentiated growth of coupling oxide and tunnel oxide at said coupling areas and tunnel areas and a seventh step involving the deposition of a layer of polysilicon constituting the floating gate.

公开(公告)号：US06876033B2

公开(公告)日：2005-04-05

申请号：US10606164

申请日：2003-06-25

申请人： Paolo Cappelletti ,  Paolo Ghezzi ,  Alfonso Maurelli ,  Loris Vendrame ,  Paola Zabberoni

发明人： Paolo Cappelletti ,  Paolo Ghezzi ,  Alfonso Maurelli ,  Loris Vendrame ,  Paola Zabberoni

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

摘要： An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

摘要翻译： 提供电可擦除和可编程的存储单元。 存储单元包括浮置栅极MOS晶体管和用于将电荷注入浮置栅极的双极晶体管。 浮置栅极晶体管具有形成在第一阱中的源极区和漏极区，沟道限定在漏极和源极区之间，控制栅极区以及在沟道和控制栅极区上延伸的浮动栅极。 双极晶体管具有形成在第一阱中的发射极区域，由第一阱构成的基极区域和由沟道组成的集电极区域。 存储单元包括与第一阱绝缘的第二阱，并且控制栅区形成在第二阱中。 本发明的另外的实施例提供了包括至少一个这样的存储单元的存储器，包括这种存储器的电子设备，以及集成存储器单元和擦除存储器单元的方法。

公开(公告)号：US5367483A

公开(公告)日：1994-11-22

申请号：US983799

申请日：1992-11-24

申请人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

发明人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  H01L21/70

CPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

摘要翻译： 一种用于制造具有单个多晶硅级别的电可擦除和可编程只读存储器单元的方法，包括使用氧化硅牺牲层在有源区上产生高厚度氧化硅层。 为了提高可靠性，保护电池的有源区域免受重的源极和漏极注入。

公开(公告)号：US06670229B2

公开(公告)日：2003-12-30

申请号：US10077288

申请日：2002-02-15

申请人： Loris Vendrame ,  Paolo Ghezzi

发明人： Loris Vendrame ,  Paolo Ghezzi

IPC分类号： H01L218238

CPC分类号： H01L29/0692 ,  H01L21/8249 ,  H01L29/7322

摘要： A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor. The bipolar transistor includes: a buried semiconductor layer having a second type of conductivity placed at a prescribed depth from the surface of said bipolar transistor, an isolation semiconductor region having the second type of conductivity, in direct contact with said buried semiconductor layer, and suitable for delimiting a portion of said substrate, forming a base region; an emitter region formed within said base region having the second type of conductivity, a base contact region of said transistor formed within said base region having the first type of conductivity, a collector contact region formed within said isolation semiconductor region having the second type of conductivity, wherein said base region has a doping concentration between 1016 and 1017 atoms/cm3.

摘要翻译： 双极晶体管是通过制造CMOS非易失性存储器件的工艺生产的，并且是集成电路的一部分。 集成电路包括具有第一导电类型的半导体衬底，形成在所述衬底中的PMOS晶体管，形成在所述衬底中的NMOS晶体管和双极晶体管。 所述双极晶体管包括：具有从所述双极晶体管的表面设置在规定深度的第二导电类型的掩埋半导体层，具有与所述掩埋半导体层直接接触的第二导电类型的隔离半导体区域， 用于限定所述衬底的一部分，形成基部区域; 形成在具有第二导电类型的所述基极区内的发射极区域，形成在具有第一导电类型的所述基极区域内的所述晶体管的基极接触区域，形成在具有第二导电类型的所述隔离半导体区域内的集电极接触区域 ，其中所述碱性区具有10 16和10 17个原子/ cm 3之间的掺杂浓度。

公开(公告)号：US5600590A

公开(公告)日：1997-02-04

申请号：US477302

申请日：1995-06-07

申请人： Paolo Ghezzi ,  Alfonso Maurelli

发明人： Paolo Ghezzi ,  Alfonso Maurelli

IPC分类号： H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866 ,  G11C13/00

CPC分类号： H01L29/66106 ,  H01L27/0629 ,  H01L29/866 ,  Y10S148/174 ,  Y10S438/983

摘要： A process for the manufacture of an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well on a single-crystal silicon substrate; a step of formation of an active area on the surface of said N type well; a step of growth of a thin gate oxide layer over said active area; a step of implantation of a first heavy dose of N type dopant into said N type well to obtain an N type region; a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region to obtain an N+contact region to both the N type well and said N type region; a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region to form a P+ region.

摘要翻译： 一种用于在快速EEPROM存储器件中制造集成式限压器和稳定器部件的方法包括在单晶硅衬底上形成N型轻掺杂阱的步骤; 在所述N型井的表面上形成活性区的步骤; 在所述有源区上生长薄栅氧化层的步骤; 将第一重剂量的N型掺杂剂注入到所述N型阱中以获得N型区域的步骤; 向所述N型区域注入高于所述第一重剂量的N型掺杂剂的第二重剂量以获得N型阱和所述N型区域的N +接触区域的步骤; 将高于所述第一重剂量的P型掺杂剂的第三重剂量植入所述N型区域以形成P +区域的步骤。