公开(公告)号：US5850360A

公开(公告)日：1998-12-15

申请号：US607779

申请日：1996-02-27

申请人： Bruno Vajana ,  Livio Baldi

发明人： Bruno Vajana ,  Livio Baldi

IPC分类号： H01L21/8238 ,  H01L27/092 ,  G11C11/34

CPC分类号： H01L21/823878 ,  H01L27/0928

摘要： A CMOS device and process are disclosed in which two types of N-channel MOS transistors are provided, one being formed in a P-well and one being formed outside the P-well where the relatively low doping concentration of P-type substrate serves as a channel defining region. This second type N-channel transistor an support higher junction voltages due to the lower p-type doping concentration than is possible for the first type N-channel transistor formed in the higher doping concentration P-well. A mask is provided to prevent boron doping in the substrate at the site of the high voltage transistor during the implantation step which defines the P-well.

摘要翻译： 公开了一种CMOS器件和工艺，其中提供两种类型的N沟道MOS晶体管，一种形成在P阱中，一种形成在P阱外部，其中P型衬底的相对低的掺杂浓度用作 一个通道定义区域。 该第二类型N沟道晶体管由于较低掺杂浓度的P型掺杂浓度而支持较高的结电压，这对于在较高掺杂浓度P阱中形成的第一型N沟道晶体管是可能的。 提供掩模以在限定P阱的注入步骤期间防止在高压晶体管的位置处的衬底中的硼掺杂。

公开(公告)号：US06465950B1

公开(公告)日：2002-10-15

申请号：US09482244

申请日：2000-01-13

申请人： Livio Baldi ,  Maria Santina Marangon

发明人： Livio Baldi ,  Maria Santina Marangon

IPC分类号： H01J6302

CPC分类号： H01J9/025 ,  H01J1/3042

摘要： The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.

摘要翻译： 限定平面FED屏幕的阴极并且面对屏幕的栅格的电荷发射材料的微尖端是管状的并且具有小的曲率半径的部分。 微尖端通过在将阴极连接层与栅格层分隔开的电介质层中形成开口，沉积导电材料层以覆盖开口的壁而获得，并各向异性地蚀刻导电材料层以形成具有发射的向内倾斜表面 提示。 随后，去除围绕微尖头的电介质层的部分。

公开(公告)号：US6000980A

公开(公告)日：1999-12-14

申请号：US807113

申请日：1996-12-13

申请人： Livio Baldi ,  Alessandro Tonti

发明人： Livio Baldi ,  Alessandro Tonti

IPC分类号： H01J9/02

CPC分类号： H01J9/025 ,  H01J2201/319

摘要： A process for forming a microtip cathode structure on a field emission display panel which avoids the need of vacuum depositing a lift-off layer for the microtip deposition overstructure in specially equipped reactors to accomplish a deposition at a grazing angle, by co-patterening the lift-off layer together with an underlying metal grid layer using a succession of different etching steps through the openings of a grid definition mask. According to an embodiment, nickel is used as lift-off material and is either wet-etched or sputter-etched before performing a plasma etch of the underlying grid metal layer. According to an alternative embodiment, the masking resist layer is used as lift-off material.

摘要翻译： 一种用于在场发射显示面板上形成微尖端阴极结构的方法，其避免真空沉积用于特别装备的反应器中的微尖端沉积过度结构的剥离层，以通过共同观察电梯来实现放电角度的沉积 使用一系列不同的蚀刻步骤通过网格定义掩模的开口与底层金属网格层一起使用。 根据一个实施例，镍用作剥离材料，并且在对下面的栅格金属层进行等离子体蚀刻之前被湿式蚀刻或溅射蚀刻。 根据替代实施例，掩模抗蚀剂层用作剥离材料。

公开(公告)号：US5589701A

公开(公告)日：1996-12-31

申请号：US486747

申请日：1995-06-07

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/823842

摘要： A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,doping the polycrystalline layer uncovered by said first mask,providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, andN+ implanting the active areas of the N-channel transistors.

摘要翻译： 一种用于在用于模拟应用的半导体集成电路中形成低阈值电压P沟道MOS晶体管的工艺，所述电路包括形成在多晶硅层中的高电阻率电阻器和具有有源区域的N沟道MOS晶体管，所述有源区域已经通过 P型阱包括以下步骤：在所述电阻器和要形成低阈值电压P沟道晶体管的半导体区域上提供第一掩模，掺杂未被所述第一掩模覆盖的多晶层，提供第二掩模 用于保护要形成所述低阈值电压P沟道晶体管的电阻器和半导体区域，以及N +注入N沟道晶体管的有源区域。

公开(公告)号：US4816883A

公开(公告)日：1989-03-28

申请号：US64480

申请日：1987-06-22

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  G11C11/34 ,  H01L27/02

CPC分类号： H01L29/7885 ,  H01L27/115

摘要： A nonvolatile, EPROM type memory cell, formed using a p-channel MOS device instead of an n-channel MOS device as customary according to the prior art, offers several advantages: improved programming characteristics, a relatively low gate voltage for writing, a lower power dissipation and above all compatability with the great majority of CMOS fabrication processes. An explanation of such surprising characteristics may be attributed to more favorable conditions of electric field during programming, i.e. during charging of the floating gate, in respect to those existing in the case of the conventional n-channel memory cell.

摘要翻译： 使用根据现有技术的通常使用p沟道MOS器件代替n沟道MOS器件的非易失性EPROM型存储单元提供了几个优点：改进的编程特性，用于写入的相对较低的栅极电压，较低的 功耗以及绝大多数CMOS制造工艺的兼容性。 关于这种令人惊奇的特性的解释可以归因于在编程期间，即在对浮动栅极充电期间相对于在常规n沟道存储单元的情况下存在的电场的更有利的条件。

公开(公告)号：US06812531B1

公开(公告)日：2004-11-02

申请号：US09303055

申请日：1999-04-30

申请人： Livio Baldi ,  Paolo Ghezzi

发明人： Livio Baldi ,  Paolo Ghezzi

IPC分类号： H01L2976

CPC分类号： H01L27/11246 ,  H01L27/112

摘要： Matrix of memory cells formed using a method allowing for a self-alignment of the respective source region with the respective field oxide layer and the respective overlying polysilicon layer of each single cell of the matrix, the matrix including at least one first ROM memory cell suitable for permanently storing a first logic level, associated with a respective row and a respective column of the matrix, the first cell including a silicon substrate of a first conductivity type over which a first isolation region and a second isolation region are formed delimiting therebetween a longitudinal stripe, a gate element extending transversally through the stripe from at least one side of the first isolation region to at least one side of the second isolation region, a third region of a second conductivity type and a fourth region of a second conductivity type formed in the substrate along the stripe, and a field oxide region adapted to prevent the formation of a conductive channel in the substrate, and at least a second ROM cell for permanently storing a second logic level, identical to the first ROM memory cell but not provided with the field oxide region.

摘要翻译： 使用允许各个源区域与相应的场氧化物层和矩阵的每个单个单元的相应的上覆多晶硅层的自对准的方法形成的存储器单元的矩阵，该矩阵包括至少一个第一ROM存储器单元 用于永久存储与矩阵的相应行和相应列相关联的第一逻辑电平，第一单元包括第一导电类型的硅衬底，在其上形成第一隔离区域和第二隔离区域，第一隔离区域和第二隔离区域之间界定纵向 条形，从第一隔离区的至少一侧横穿条带延伸至第二隔离区的至少一侧的栅极元件，形成第二导电类型的第三区域和第二导电类型的第四区域 沿着条带的衬底，以及适于防止在子层中形成导电沟道的场氧化物区域 并且至少第二ROM单元用于永久地存储第二逻辑电平，与第一ROM存储器单元相同但不具有场氧化物区域。

公开(公告)号：US5708451A

公开(公告)日：1998-01-13

申请号：US681099

申请日：1996-07-22

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： G09G3/22 ,  H01J31/12 ,  G09G3/36

CPC分类号： G09G3/22 ,  H01J31/127 ,  G09G2320/0285 ,  G09G2320/043

摘要： Nonuniformities of luminance characteristics in a field emission display (FED) are compensated pixel by pixel by storing a matrix of correction values, determined by testing, and by applying a corrected drive signal through the relative column drive stages. The individual pixel's correction factor that is applied to the corresponding video signal may be stored in digital or analog form in a nonvolatile memory array. Various embodiments are described including the use of a second updatable RAM array wherein pixel's correction factors are calculated and stored at every power-on to provide an opportunity of trimming-up the luminance of the display for compensating long term decline of luminance due to the phosphors ageing process.

摘要翻译： 通过存储通过测试确定的校正值的矩阵以及通过相对列驱动级施加校正的驱动信号，逐像素地补偿场发射显示（FED）中的亮度特性的不均匀性。 应用于相应视频信号的单个像素的校正因子可以以数字或模拟形式存储在非易失性存储器阵列中。 描述了各种实施例，其包括使用第二可更新RAM阵列，其中在每次上电时计算和存储像素的校正因子，以提供修整显示器亮度的机会，以补偿由于荧光体引起的长期亮度下降 老化过程。

公开(公告)号：US4968645A

公开(公告)日：1990-11-06

申请号：US289391

申请日：1988-12-15

申请人： Livio Baldi ,  Paolo G. Cappelletti ,  Franco Maggioni

发明人： Livio Baldi ,  Paolo G. Cappelletti ,  Franco Maggioni

IPC分类号： H01L27/092 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/52 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L27/0688 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/106 ,  Y10S148/136

摘要： A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer of polycrystalline silicon, a layer of a silicide of a refractory metal overlying said polycrystalline silicon layer, and regions of preset area and preset paths formed in the polycrystalline silicon layer and the silicide layer; the preset area regions and preset paths forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.

摘要翻译： MOS或CMOS型的单片集成电路包括多晶硅的中间层，覆盖所述多晶硅层的难熔金属的硅化物层，以及形成在多晶硅层中的预设区域和预设路径的区域，以及 硅化物层 预设区域和预置路径分别形成用于中间连接水平的高电阻率电阻和低电阻率互连线。

公开(公告)号：US07125807B2

公开(公告)日：2006-10-24

申请号：US10746878

申请日：2003-12-23

申请人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

发明人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

IPC分类号： H01L21/302 ,  H01B13/00

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.

摘要翻译： 半导体衬底具有由绝缘层的部分限定的有源区域。 在衬底上形成隧道氧化物薄层，然后沉积第一层导电材料。 通过限定浮动栅极区域在其上制造非易失性存储器单元。 这些浮动栅极区域的定义涉及限定第一层导电材料，以便形成由有缺陷条纹的有源区域交替的一对有源区域之上的多个交替条纹。 然后在交替条纹的侧壁的遮蔽物中形成间隔物。 然后第二层导电材料与第一层导电材料一起沉积。 然后选择性地去除间隔物。

公开(公告)号：US20050042812A1

公开(公告)日：2005-02-24

申请号：US10890529

申请日：2004-07-12

申请人： Daniela Brazzelli ,  Livio Baldi ,  Giorgio Servalli

发明人： Daniela Brazzelli ,  Livio Baldi ,  Giorgio Servalli

IPC分类号： H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/76229

摘要： Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of realising a digging in the substrate and in the field oxide of said first device area.

摘要翻译： 本发明的实施例涉及一种用于在单片集成半导体电子器件中制造具有不同深度的隔离结构的方法。 根据本发明实施例的发明方法包括：在半导体材料衬底上限定有源区的第一步骤;通过在所述衬底中实现沟槽然后用场氧化物填充来形成隔离结构的第二步骤;第三步骤， 光刻至少第一装置区域，以及第四步骤，在所述基板和所述第一装置区域的场氧化物中实现挖掘。