METHOD FOR PERFORMING HANDOVER BY CONSIDERING QUALITY OF SERVICE IN BROADBAND MOBILE COMMUNICATION SYSTEM AND SYSTEM FOR PROVIDING THE SAME
    11.
    发明申请
    METHOD FOR PERFORMING HANDOVER BY CONSIDERING QUALITY OF SERVICE IN BROADBAND MOBILE COMMUNICATION SYSTEM AND SYSTEM FOR PROVIDING THE SAME 有权
    通过考虑宽带移动通信系统中的服务质量来执行切换的方法及其提供的系统

    公开(公告)号:US20080240043A1

    公开(公告)日:2008-10-02

    申请号:US12050341

    申请日:2008-03-18

    CPC classification number: H04W36/30 H04W36/26

    Abstract: A system and method for performing a handover of a mobile station (MS) by considering Quality of Service (QoS) in a broadband mobile communication system. The method can include the steps of: receiving information about one or more neighbor base stations and reception strengths for the neighbor base stations from a Serving Radio Access System (RAS) currently communicating with the MS; extracting a value of a specific field from the received information about the neighbor base stations; combining the extracted value of the specific field with the reception strengths to thereby obtain combined values, and selecting a maximum value among the combined values; and transmitting a handover (handoff) request message to a base station corresponding to the selected maximum value. The system includes an MS that analyzes information about neighbor stations received in a Mobile Neighbor Base-station Advertisement (MOB_NBR_ADV) message to select a target RAS.

    Abstract translation: 一种通过考虑宽带移动通信系统中的服务质量(QoS)来执行移动台(MS)的切换的系统和方法。 该方法可以包括以下步骤:从当前与MS通信的服务无线电接入系统(RAS)接收关于一个或多个相邻基站的信息和相邻基​​站的接收强度; 从接收到的关于邻近基站的信息中提取特定字段的值; 将所提取的特定字段的值与接收强度组合,从而获得组合值,并且选择组合值中的最大值; 以及向对应于所选择的最大值的基站发送切换(切换)请求消息。 该系统包括分析在移动邻居基站广播(MOB_NBR_ADV)消息中接收的关于相邻站的信息以选择目标RAS的MS。

    VERTICAL MEMORY DEVICES
    12.
    发明申请
    VERTICAL MEMORY DEVICES 有权
    垂直存储器件

    公开(公告)号:US20150221666A1

    公开(公告)日:2015-08-06

    申请号:US14605529

    申请日:2015-01-26

    Applicant: Chang-Hyun LEE

    Inventor: Chang-Hyun LEE

    Abstract: According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance layer, a plurality of vertical channels on the channel layer, and a plurality of gate lines. The vertical channels extend in a first direction that is perpendicular with respect to a top surface of the channel layer. The gate lines surround outer sidewalls of the vertical channels, and are stacked in the first direction and are spaced apart from each other.

    Abstract translation: 根据示例实施例,垂直存储器件包括在下绝缘层上的低电阻层,低电阻层上的沟道层,沟道层上的多个垂直沟道以及多条栅极线。 垂直通道在相对于沟道层的顶表面垂直的第一方向上延伸。 栅极线围绕垂直通道的外侧壁,并且沿第一方向堆叠并且彼此间隔开。

    VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING A METAL GATE AND METHODS OF FORMING THE SAME
    13.
    发明申请
    VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING A METAL GATE AND METHODS OF FORMING THE SAME 有权
    包括金属门的垂直型半导体器件及其形成方法

    公开(公告)号:US20140203346A1

    公开(公告)日:2014-07-24

    申请号:US14132425

    申请日:2013-12-18

    Applicant: Chang-Hyun LEE

    Inventor: Chang-Hyun LEE

    Abstract: Vertical type semiconductor devices including a metal gate and methods of forming the vertical type semiconductor devices are provided. The vertical type semiconductor devices may include a channel pattern. The vertical type semiconductor devices may also include first and second gate patterns sequentially stacked on a sidewall of the channel pattern. The first and second gate pattern may include first and second metal elements, respectively and the second gate pattern may have a resistance lower than a resistance of the first gate pattern.

    Abstract translation: 提供了包括金属栅极的垂直型半导体器件和形成垂直型半导体器件的方法。 垂直型半导体器件可以包括沟道图案。 垂直型半导体器件还可以包括顺序地堆叠在沟道图案的侧壁上的第一和第二栅极图案。 第一和第二栅极图案可以分别包括第一和第二金属元件,并且第二栅极图案可以具有比第一栅极图案的电阻低的电阻。

    NAND FLASH MEMORY DEVICES
    14.
    发明申请
    NAND FLASH MEMORY DEVICES 审中-公开
    NAND闪存存储器件

    公开(公告)号:US20130092996A1

    公开(公告)日:2013-04-18

    申请号:US13552877

    申请日:2012-07-19

    CPC classification number: H01L27/11524

    Abstract: NAND flash memory device includes a common bit line, a first cell string including a first string selecting transistor having a first gate length, a second string selecting transistor having a second gate length, first cell transistors each having a third gate length and a first ground selecting transistor having a fourth gate length, a second cell string including a third string selecting transistor having the first gate length, a fourth string selecting transistor having the second gate length, second cell transistors each having the third gate length and a second ground selecting transistor having the fourth gate length and a common source line commonly connected to end portions of the first and second ground selecting transistors included in the first and second cell strings. At least one of the first gate length and the second gate length is smaller than the fourth gate length.

    Abstract translation: NAND闪存器件包括公共位线,第一单元串,包括具有第一栅极长度的第一串选择晶体管,具有第二栅极长度的第二串选择晶体管,每个具有第三栅极长度的第一单元晶体管和第一栅极 选择具有第四栅极长度的晶体管,第二单元串,包括具有第一栅极长度的第三串选择晶体管,具有第二栅极长度的第四串选择晶体管,每个具有第三栅极长度的第二单元晶体管和第二栅极选择晶体管 具有第四栅极长度和公共源极线,共同连接到包括在第一和第二单元串中的第一和第二接地选择晶体管的端部。 第一栅极长度和第二栅极长度中的至少一个小于第四栅极长度。

    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    16.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号:US20150137216A1

    公开(公告)日:2015-05-21

    申请号:US14534181

    申请日:2014-11-06

    Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

    Abstract translation: 垂直存储器件包括衬底,通道,栅极线和连接部分。 多个通道在与基板的顶表面垂直的第一方向上延伸。 多个栅极线在第一方向上被堆叠以彼此间隔开并且在第二长度方向上延伸,每个栅极线与通道组的每组通道的每个通道的外侧壁相交。 栅极线形成包括多个垂直电平的阶梯结构。 连接部分连接位于相同垂直高度的多条栅极线的一组栅极线,该连接部分从栅极线组的栅极线延伸的第二方向发散。

    METHOD AND APPARATUS FOR CODING VIDEO IMAGE
    18.
    发明申请
    METHOD AND APPARATUS FOR CODING VIDEO IMAGE 审中-公开
    编码视频图像的方法和装置

    公开(公告)号:US20100166075A1

    公开(公告)日:2010-07-01

    申请号:US12649467

    申请日:2009-12-30

    CPC classification number: H04N19/11 H04N19/119 H04N19/147 H04N19/176 H04N19/61

    Abstract: A method and apparatus for coding a video image is provided, in which a first macro block is coded with intra coding modes, the number of which corresponds to the first macro block, a first intra coding mode having a minimum value and a first minimum value to which the first intra coding mode is applied are acquired, the first minimum value is compared with a threshold that is set for fast coding mode search, and it is determined whether to code a second macro block with intra coding modes, the number of which corresponds to the second macro block, based on the comparison.

    Abstract translation: 提供了一种用于对视频图像进行编码的方法和装置,其中第一宏块以帧内编码模式编码,其编号对应于第一宏块,第一帧内编码模式具有最小值和第一最小值 获取应用了第一帧内编码模式的第一最小值与对于快速编码模式搜索设定的阈值进行比较,并且确定是否以帧内编码模式对第二宏块进行编码,其编号 对应于第二个宏块,基于比较。

    METHOD AND APPARATUS FOR COMPRESSING A REFERENCE FRAME IN ENCODING/DECODING MOVING IMAGES
    19.
    发明申请
    METHOD AND APPARATUS FOR COMPRESSING A REFERENCE FRAME IN ENCODING/DECODING MOVING IMAGES 审中-公开
    用于在编码/解码移动图像中压缩参考帧的方法和装置

    公开(公告)号:US20100027617A1

    公开(公告)日:2010-02-04

    申请号:US12511497

    申请日:2009-07-29

    CPC classification number: H04N19/115 H04N19/149 H04N19/176

    Abstract: Provided is a method of compressing a reference frame in encoding or decoding moving images. A reference frame to be compressed is divided into basic processing blocks. The basic processing blocks are divided into sub-blocks. A maximum value and a minimum value of pixels within each sub-block are calculated. A necessary bit length needed for compression of each sub-block is obtained based on a difference between the maximum value and the minimum value. An average bit length of the sub-blocks within the basic processing block is calculated based on the calculated necessary bit lengths of the sub-blocks. Bits are variably allocated to each sub-block by adjusting the necessary bit length of each sub-block so that the average bit length of the sub-blocks within a corresponding basic processing block is less than or equal to a preset required bit length. Each sub-block is compressed to the allocated bits.

    Abstract translation: 提供了一种在编码或解码运动图像中压缩参考帧的方法。 要压缩的参考帧被分为基本处理块。 基本处理块分为子块。 计算每个子块内像素的最大值和最小值。 基于最大值和最小值之间的差异,获得每个子块的压缩所需的必要位长度。 基于所计算的子块的必要位长度来计算基本处理块内的子块的平均位长度。 通过调整每个子块的必要比特长度,可以将比特分配给每个子块,使得对应的基本处理块内的子块的平均比特长度小于或等于预设的所需比特长度。 每个子块被压缩到分配的位。

Patent Agency Ranking