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175 条记录 (耗时 0.036 秒)

    Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
    11.
    发明授权
    Transforming non-contiguous instruction specifiers to contiguous instruction specifiers 有权
    将不连续的指令说明符转换为连续的指令说明符

    公开(公告)号：US09280347B2

    公开(公告)日：2016-03-08

    申请号：US13421657

    申请日：2012-03-15

    申请人： Michael K. Gschwind

    发明人： Michael K. Gschwind

    IPC分类号： G06F9/30 ,  G06F9/45 ,  G06F9/455

    CPC分类号： G06F9/30181 ,  G06F8/52 ,  G06F9/30036 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/30174 ,  G06F9/342 ,  G06F9/45516

    摘要： Emulation of instructions that include non-contiguous specifiers is facilitated. A non-contiguous specifier specifies a resource of an instruction, such as a register, using multiple fields of the instruction. For example, multiple fields of the instruction (e.g., two fields) include bits that together designate a particular register to be used by the instruction. Non-contiguous specifiers of instructions defined in one computer system architecture are transformed to contiguous specifiers usable by instructions defined in another computer system architecture. The instructions defined in the another computer system architecture emulate the instructions defined for the one computer system architecture.

    摘要翻译： 包含非连续说明符的指令的仿真是有利的。 不连续的说明符使用指令的多个字段来指定诸如寄存器的指令的资源。 例如，指令的多个字段（例如，两个字段）包括一起指定要由指令使用的特定寄存器的位。 在一个计算机系统架构中定义的指令的不连续的说明符被转换为可由另一计算机系统架构中定义的指令使用的连续的说明符。 在另一计算机系统架构中定义的指令模拟了针对一个计算机系统架构所定义的指令。

    Hybrid address translation
    12.
    发明授权
    Hybrid address translation 有权

    公开(公告)号：US09256550B2

    公开(公告)日：2016-02-09

    申请号：US13432381

    申请日：2012-03-28

    申请人： Anthony J. Bybell ,  Michael K. Gschwind

    发明人： Anthony J. Bybell ,  Michael K. Gschwind

    IPC分类号： G06F12/10 ,  G06F12/02

    CPC分类号： G06F12/1027 ,  G06F12/0292 ,  G06F12/1018 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/651 ,  G06F2212/684

    摘要： Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.

    Optimizing subroutine calls based on architecture level of called subroutine
    14.
    发明授权
    Optimizing subroutine calls based on architecture level of called subroutine 有权
    根据调用子程序的架构级别优化子程序调用

    公开(公告)号：US09063759B2

    公开(公告)日：2015-06-23

    申请号：US13432393

    申请日：2012-03-28

    申请人： Michael K. Gschwind

    发明人： Michael K. Gschwind

    IPC分类号： G06F9/44 ,  G06F9/445

    CPC分类号： G06F9/44521 ,  G06F9/4484

    摘要： A technique is provided for generating stubs. A processing circuit receives a call to a called function. The processing circuit retrieves a called function property of the called function. The processing circuit generates a stub for the called function based on the called function property.

    摘要翻译： 提供了一种用于生成存根的技术。 处理电路接收对被叫功能的呼叫。 处理电路检索被叫函数的被叫函数属性。 处理电路基于被叫函数特性生成被叫函数的存根。

    Vector loads with multiple vector elements from a same cache line in a scattered load operation
    15.
    发明授权
    Vector loads with multiple vector elements from a same cache line in a scattered load operation 有权
    在分散加载操作中，来自相同高速缓存行的多个向量元素的向量加载

    公开(公告)号：US08904153B2

    公开(公告)日：2014-12-02

    申请号：US12876321

    申请日：2010-09-07

    申请人： Alexandre E. Eichenberger ,  Michael K. Gschwind ,  Valentina Salapura

    发明人： Alexandre E. Eichenberger ,  Michael K. Gschwind ,  Valentina Salapura

    IPC分类号： G06F9/345 ,  G06F9/30 ,  G06F9/38 ,  G06F15/80

    CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3857 ,  G06F15/8069

    摘要： Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of data element address portions that specify a plurality of data elements to be accessed using the single extended address. Each of the plurality of data element address portions is provided to corresponding data element selector logic units of the cache memory. Each data element selector logic unit in the cache memory selects a corresponding data element from a cache line buffer based on a corresponding data element address portion provided to the data element selector logic unit. Each data element selector logic unit outputs the corresponding data element for use by the processor.

    摘要翻译： 提供了执行分散加载操作的机构。 利用这些机制，扩展地址被接收在处理器的高速缓冲存储器中。 扩展地址具有多个数据元素地址部分，其指定使用单个扩展地址来访问的多个数据元素。 多个数据元素地址部分中的每一个被提供给高速缓冲存储器的相应数据元素选择器逻辑单元。 高速缓冲存储器中的每个数据元素选择器逻辑单元基于提供给数据元素选择器逻辑单元的相应数据元素地址部分从高速缓存行缓冲器中选择相应的数据元素。 每个数据元素选择器逻辑单元输出相应的数据元素供处理器使用。

    MANAGING REGISTER PAIRING
    16.
    发明申请
    MANAGING REGISTER PAIRING 有权
    管理注册配对

    公开(公告)号：US20140025929A1

    公开(公告)日：2014-01-23

    申请号：US13552109

    申请日：2012-07-18

    申请人： Jonathan D. Bradbury ,  Michael K. Gschwind

    发明人： Jonathan D. Bradbury ,  Michael K. Gschwind

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30112 ,  G06F9/30141 ,  G06F9/3838

    摘要： Embodiments relate to reducing a number of read ports for register pairs. An aspect includes maintaining an active pairing indicator that is configured to have a first value or a second value. The first value indicates that the wide operand is stored in a wide register. The second value indicates that the wide operand is not stored in the wide register. The operand is read from either the wide register or a pair of registers based on the active pairing indicator. The active pairing indicator and the values of the set of wide registers are stored to a storage based on a request to store a register pairing status. A saved pairing indicator and saved values of the set of wide registers is loaded from the storage respectively into an active pairing register and wide registers.

    摘要翻译： 实施例涉及减少用于寄存器对的多个读端口。 一个方面包括维持被配置为具有第一值或第二值的活动配对指示符。 第一个值表示宽操作数存储在一个宽的寄存器中。 第二个值表示宽操作数不存储在宽寄存器中。 基于活动配对指示器，从宽寄存器或一对寄存器读取操作数。 基于存储寄存器配对状态的请求，将活动配对指示符和宽寄存器组的值存储到存储器中。 一组保存的配对指示器和一组宽寄存器的保存值分别从存储器加载到有源配对寄存器和宽寄存器中。

    PERFORMING PREDECODE-TIME OPTIMIZED INSTRUCTIONS IN CONJUNCTION WITH PREDECODE TIME OPTIMIZED INSTRUCTION SEQUENCE CACHING
    17.
    发明申请
    PERFORMING PREDECODE-TIME OPTIMIZED INSTRUCTIONS IN CONJUNCTION WITH PREDECODE TIME OPTIMIZED INSTRUCTION SEQUENCE CACHING 有权
    与预定时间优化的指令序列缓存执行预定时间优化的指令

    公开(公告)号：US20130262821A1

    公开(公告)日：2013-10-03

    申请号：US13432357

    申请日：2012-03-28

    申请人： Michael K. Gschwind ,  Valentina Salapura

    发明人： Michael K. Gschwind ,  Valentina Salapura

    IPC分类号： G06F9/30 ,  G06F9/312

    CPC分类号： G06F9/382 ,  G06F9/3017 ,  G06F9/3808 ,  G06F9/384

    摘要： A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response to the determining that the first instruction and second instruction can be optimized, the method includes, preforming a pre-decode optimization on the instruction sequence and generating a new second instruction, wherein the new second instruction is not dependent on a target operand of the first instruction and storing a pre-decoded first instruction and a pre-decoded new second instruction in an instruction cache. In response to determining that the first instruction and second instruction can not be optimized, the method includes, storing the pre-decoded first instruction and a pre-decoded second instruction in the instruction cache.

    摘要翻译： 一种执行预解码时间优化指令并结合预解码时间优化指令序列缓存的方法。 该方法包括接收指令序列的第一指令和指令序列的第二指令，并且确定是否可以优化第一指令和第二指令。 响应于确定可以优化第一指令和第二指令，该方法包括：对指令序列执行预解码优化并产生新的第二指令，其中新的第二指令不依赖于目标操作数 所述第一指令并将预解码的第一指令和预解码的新的第二指令存储在指令高速缓存中。 响应于确定第一指令和第二指令不能被优化，该方法包括：将预解码的第一指令和预解码的第二指令存储在指令高速缓存中。