公开(公告)号：US20080154140A1

公开(公告)日：2008-06-26

申请号：US11783447

申请日：2007-04-10

申请人： Chien-Cheng Chang ,  Po-Hsiang Tsui ,  Chien-Chung Chang ,  King-Jen Chang ,  Chung-Li Wang ,  Juey-Jen Hwang ,  Chin-Chou Chu ,  Chiung-Nien Chen ,  Lian-Yu Lin

发明人： Chien-Cheng Chang ,  Po-Hsiang Tsui ,  Chien-Chung Chang ,  King-Jen Chang ,  Chung-Li Wang ,  Juey-Jen Hwang ,  Chin-Chou Chu ,  Chiung-Nien Chen ,  Lian-Yu Lin

IPC分类号： A61B5/02

CPC分类号： A61B5/022 ,  A61B5/02007 ,  A61B5/02116 ,  A61B5/6822

摘要： A carotid pulse measurement device provided for measuring carotid pulse of a user's neck includes a band, an artery-pressing air cell, an inflating/deflating device, and a pressure detection unit. The band functions to surround the user's neck. The air cell is arranged in the band and is fluidly connected to the inflating/deflating device for selectively inflating/deflating the air cell. The pressure detection unit detects variation of pressure inside the air cell. To use the measurement device, the band is put around the user's neck with the air cell positioned exactly corresponding to the carotid artery of the neck so that the pressure detection device detects the pressure variation and generates a digital pulse signal, which is employed to calculate arteriosclerosis index of the user for evaluation the degree of arteriosclerosis of the user.

摘要翻译： 用于测量使用者颈部颈动脉脉搏的颈动脉搏动测量装置包括带，动脉压气囊，充气/放气装置和压力检测单元。 乐队的功能是围绕用户的脖子。 气囊布置在带中并且流体地连接到充气/放气装置，用于选择性地使空气室膨胀/放气。 压力检测单元检测气囊内的压力变化。 为了使用测量装置，将带放在用户颈部周围，其中气囊正好对应于颈部的颈动脉，使得压力检测装置检测压力变化并产生用于计算的数字脉冲信号 用户的动脉硬化指数用于评估用户的动脉硬化程度。

公开(公告)号：US07059351B1

公开(公告)日：2006-06-13

申请号：US11293137

申请日：2005-12-05

申请人： Chin-Chou Chu ,  Chien-Fu Chen ,  Chun-Fei Kung ,  Chien-Cheng Chang ,  Fan-Gang Tseng

发明人： Chin-Chou Chu ,  Chien-Fu Chen ,  Chun-Fei Kung ,  Chien-Cheng Chang ,  Fan-Gang Tseng

IPC分类号： F15C1/04 ,  F15C1/06

CPC分类号： B01L3/50273 ,  B01F5/0646 ,  B01F5/0647 ,  B01F13/0084 ,  B01F13/0086 ,  B01L3/502746 ,  B01L3/502784 ,  B01L2300/028 ,  B01L2300/0816 ,  B01L2300/0867 ,  B01L2400/0406 ,  B01L2400/086 ,  Y10T137/2076 ,  Y10T137/2082 ,  Y10T137/212 ,  Y10T137/218 ,  Y10T137/2224

摘要： A liquid transportation device includes a working board, a working liquid, a liquid channel and a cover board, wherein the liquid channel is formed on a top surface of the working board, the covering board is fully covered the liquid channel, the liquid channel composed of a material substantially tending to the liquid, and the covering board is composed of a material substantially phobic to the liquid. The working liquid flows within the liquid channel in guidance of the deviation of surface tension between the liquid channel to the working liquid, and the covering board to the working liquid, so that the working liquid is transported within the liquid channel without any external power.

摘要翻译： 液体输送装置包括工作板，工作液体，液体通道和盖板，其中液体通道形成在工作板的顶表面上，覆盖板完全覆盖液体通道，液体通道组成 基本上倾向于液体的材料，并且覆盖板由基本上与液体相邻的材料组成。 在液体通道与工作液体之间的表面张力偏离和工作液体的覆盖板的引导下，工作液体在液体通道内流动，使得工作液体在液体通道内没有任何外部动力传送。

公开(公告)号：US07010707B2

公开(公告)日：2006-03-07

申请号：US10223274

申请日：2002-08-19

申请人： Ming-Hsun Hsu ,  Chien-Cheng Chang ,  Yu-En Tzeng

发明人： Ming-Hsun Hsu ,  Chien-Cheng Chang ,  Yu-En Tzeng

IPC分类号： G06F1/26

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  Y02D10/171

摘要： A method for saving electrical power for a physical layer (PHY) device including a plurality of sub-circuits is disclosed. The method includes the steps of outputting a plurality of link pulses, asserting a plurality of disabling signals between two adjacent link pulses for disabling the sub-circuits, respectively, and deasserting the disabling signals for enabling the sub-circuits, respectively. The disabling signals are asserted separately for disabling the sub-circuits at different time points. A physical layer device for use in a chip for saving electrical power is also disclosed.

摘要翻译： 公开了一种用于节省包括多个子电路的物理层（PHY）装置的电力的方法。 该方法包括以下步骤：输出多个链路脉冲，分别在两个相邻链路脉冲之间确定多个禁用信号，以分别禁止子电路，以及分别禁用用于使能子电路的禁用信号。 单独断言禁用信号，以在不同的时间点禁用子电路。 还公开了一种用于节省电力的芯片中的物理层装置。

公开(公告)号：US20130045362A1

公开(公告)日：2013-02-21

申请号：US13592254

申请日：2012-08-22

申请人： Chien-Cheng Chang ,  Yu-Chun Chien ,  Da-Shan Lin ,  Han-Hsiang Lin

发明人： Chien-Cheng Chang ,  Yu-Chun Chien ,  Da-Shan Lin ,  Han-Hsiang Lin

IPC分类号： G03F7/20 ,  H01B1/02

CPC分类号： G03F7/027 ,  G03F7/203 ,  Y10T428/24355

摘要： A method for making a conductive laminate includes: (a) forming a photocurable layer on a substrate, the photocurable layer including at least one photocurable prepolymer that has a plurality of reactive functional groups and that has a functional group equivalent weight ranging from 70 to 700 g/mol; (b) covering partially the photocurable layer using a patterned mask; (c) exposing the photocurable layer through the patterned mask using a first light source; (d) removing the patterned mask; (e) exposing the photocurable layer to a second light source to cure second regions of the photocurable layer which have not been cured, so as to form a microstructure; and (f) forming a conductive layer on the microstructure.

摘要翻译： 制造导电性层叠体的方法包括：（a）在基材上形成光固化层，所述光固化层包含至少一种具有多个反应性官能团并具有70〜700的官能团当量的光固化性预聚物 g / mol; （b）使用图案化掩模部分地覆盖光固化层; （c）使用第一光源将可光固化层曝光通过图案化掩模; （d）去除图案化掩模; （e）将光固化层暴露于第二光源以固化未固化的光固化层的第二区域，以形成微结构; 和（f）在微结构上形成导电层。

公开(公告)号：US07539913B2

公开(公告)日：2009-05-26

申请号：US11428585

申请日：2006-07-05

申请人： Chien-Cheng Chang ,  Cheng-Yuan Wu

发明人： Chien-Cheng Chang ,  Cheng-Yuan Wu

IPC分类号： G01R31/28

CPC分类号： G01R31/31722 ,  G01R31/31723

摘要： Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module and a selection device. The storage device stores first, second, third and fourth N-bit groups of a test pattern separately according to a loading signal and an address selection signal. The first multiplexing module is coupled to the storage device and a first digital logic circuit module, for parallel transmitting the first, second, third and fourth N-bit groups which will be received and executed by the first digital logic circuit module to parallel generate first, second and third M-bit groups. The selection device is coupled to the first digital logic circuit module for sequentially selecting one of the first, second and third M-bit groups to output a first test result according to the address selection signal.

摘要翻译： 用于测试集成电路芯片的数字逻辑电路模块的电路和方法。 电路包括存储装置，第一复用模块和选择装置。 存储装置根据加载信号和地址选择信号分别存储测试图案的第一，第二，第三和第四N比特组。 第一复用模块耦合到存储设备和第一数字逻辑电路模块，用于并行发送将被第一数字逻辑电路模块接收和执行的第一，第二，第三和第四N位组，以并行产生 ，第二和第三M位组。 选择装置耦合到第一数字逻辑电路模块，用于依次选择第一，第二和第三M位组中的一个，以根据地址选择信号输出第一测试结果。

公开(公告)号：US07359391B2

公开(公告)日：2008-04-15

申请号：US10604684

申请日：2003-08-10

申请人： Ming-Hsun Hsu ,  Chien-Cheng Chang

发明人： Ming-Hsun Hsu ,  Chien-Cheng Chang

IPC分类号： H04L12/28

CPC分类号： H04L25/03866

摘要： A multi-port network interface circuit and related control method. The network interface circuit has a plurality of PHY circuits, each of the PHY circuit is used for transmitting signals to a plurality of corresponding network nodes via different ports. Each of the PHY circuits scrambles signals transmitted at different ports with different seeds, and the network interface circuit resets different PHY circuits at different times such that each of the PHY circuits starts to transmit signals at a different time.

摘要翻译： 一种多端口网络接口电路及相关控制方法。 网络接口电路具有多个PHY电路，每个PHY电路用于经由不同的端口向多个相应的网络节点发送信号。 每个PHY电路用不同的种子对在不同端口发送的信号进行加扰，并且网络接口电路在不同的时间重置不同的PHY电路，使得每个PHY电路在不同的时间开始发送信号。

公开(公告)号：US20080022168A1

公开(公告)日：2008-01-24

申请号：US11428585

申请日：2006-07-05

申请人： Chien-Cheng Chang ,  Cheng-Yuan WU

发明人： Chien-Cheng Chang ,  Cheng-Yuan WU

IPC分类号： G01R31/28

CPC分类号： G01R31/31722 ,  G01R31/31723

摘要： Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module and a selection device. The storage device stores first, second, third and fourth N-bit groups of a test pattern separately according to a loading signal and an address selection signal. The first multiplexing module is coupled to the storage device and a first digital logic circuit module, for parallel transmitting the first, second, third and fourth N-bit groups which will be received and executed by the first digital logic circuit module to parallel generate first, second and third M-bit groups. The selection device is coupled to the first digital logic circuit module for sequentially selecting one of the first, second and third M-bit groups to output a first test result according to the address selection signal.

摘要翻译： 用于测试集成电路芯片的数字逻辑电路模块的电路和方法。 电路包括存储装置，第一复用模块和选择装置。 存储装置根据加载信号和地址选择信号分别存储测试图案的第一，第二，第三和第四N比特组。 第一复用模块耦合到存储设备和第一数字逻辑电路模块，用于并行发送将被第一数字逻辑电路模块接收和执行的第一，第二，第三和第四N位组，以并行产生 ，第二和第三M位组。 选择装置耦合到第一数字逻辑电路模块，用于依次选择第一，第二和第三M位组中的一个，以根据地址选择信号输出第一测试结果。

公开(公告)号：US20050008036A1

公开(公告)日：2005-01-13

申请号：US10604684

申请日：2003-08-10

申请人： Ming-Hsun Hsu ,  Chien-Cheng Chang

发明人： Ming-Hsun Hsu ,  Chien-Cheng Chang

IPC分类号： H04L12/54 ,  H04L12/66 ,  H04L25/03

CPC分类号： H04L25/03866

摘要： A multi-port network interface circuit and related control method. The network interface circuit has a plurality of PHY circuits, each of the PHY circuit is used for transmitting signals to a plurality of corresponding network nodes via different ports. Each of the PHY circuits scrambles signals transmitted at different ports with different seeds, and the network interface circuit resets different PHY circuits at different times such that each of the PHY circuits starts to transmit signals at a different time.

摘要翻译： 一种多端口网络接口电路及相关控制方法。 网络接口电路具有多个PHY电路，每个PHY电路用于经由不同的端口向多个相应的网络节点发送信号。 每个PHY电路用不同的种子对在不同端口发送的信号进行加扰，并且网络接口电路在不同的时间重置不同的PHY电路，使得每个PHY电路在不同的时间开始发送信号。