公开(公告)号：US08872280B2

公开(公告)日：2014-10-28

申请号：US13562322

申请日：2012-07-31

Applicant: Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

IPC: H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/51 ,  H01L29/66818 ,  H01L29/785

Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。

公开(公告)号：USD712590S1

公开(公告)日：2014-09-02

申请号：US29473466

申请日：2013-11-22

Applicant: Chien-Ting Lin

Designer： Chien-Ting Lin

公开(公告)号：US08722501B2

公开(公告)日：2014-05-13

申请号：US13275337

申请日：2011-10-18

Applicant: Shih-Hung Tsai ,  Chien-Liang Lin ,  Chien-Ting Lin ,  Ssu-I Fu ,  Ying-Tsung Chen

Inventor： Shih-Hung Tsai ,  Chien-Liang Lin ,  Chien-Ting Lin ,  Ssu-I Fu ,  Ying-Tsung Chen

IPC: H01L21/336

CPC classification number: H01L29/66795

Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.

Abstract translation: 一种制造多栅极晶体管器件的方法包括：提供具有图案化半导体层，栅极电介质层和顺序地形成在其上的栅极层的半导体衬底，形成依次具有第一绝缘层和第二绝缘层的覆盖层 图案化半导体层和栅极层，去除多个绝缘层的一部分以同时在栅极层周围形成第一间隔物，以及围绕图案化半导体层形成第二间隔物，去除第二间隔物以暴露第一绝缘层的一部分 覆盖图案化的半导体层并且同时移除第一间隔物的一部分以形成围绕栅极层的第三间隔物，以及去除暴露的第一绝缘层以暴露图案化的半导体层。

公开(公告)号：US08669618B2

公开(公告)日：2014-03-11

申请号：US13326342

申请日：2011-12-15

Applicant: Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

Inventor： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

IPC: H01L21/70

CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。

公开(公告)号：US08664060B2

公开(公告)日：2014-03-04

申请号：US13367382

申请日：2012-02-07

Applicant: An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

IPC: H01L29/78

CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.

Abstract translation: 一种半导体结构及其制造方法，包括以下步骤：提供衬底，在所述衬底上形成至少一个鳍结构，形成覆盖所述鳍结构的栅极，形成覆盖所述鳍结构的多个外延结构， 拉回过程以减小所述栅极的临界尺寸（CD）并分离所述栅极和所述外延结构，在所述鳍结构中形成轻掺杂的漏极（LDD），以及在所述栅极和所述鳍结构上形成间隔物。

公开(公告)号：US08574990B2

公开(公告)日：2013-11-05

申请号：US13033616

申请日：2011-02-24

Applicant: Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Shui-Yen Lu ,  Pei-Yu Chou ,  Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chan-Lon Yang ,  Teng-Chun Tsai ,  Chun-Hsien Lin

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Shui-Yen Lu ,  Pei-Yu Chou ,  Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chan-Lon Yang ,  Teng-Chun Tsai ,  Chun-Hsien Lin

IPC: H01L21/00

CPC classification number: H01L29/66545 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966

Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.

Abstract translation: 本发明提供一种制造具有金属栅极的半导体器件的方法。 首先，提供基板。 具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。 去除第一牺牲栅极以形成第一沟槽，然后在第一沟槽中形成第一金属层和第一材料层。 接下来，第一金属层和第一材料层变平。 去除第二牺牲栅极以形成第二沟槽，然后在第二沟槽中形成第二金属层和第二材料层。 最后，第二金属层和第二材料层变平。

公开(公告)号：US08528869B2

公开(公告)日：2013-09-10

申请号：US13280325

申请日：2011-10-24

Applicant: Chien-Ting Lin

Inventor： Chien-Ting Lin

IPC: F16M13/00

CPC classification number: F16M11/26 ,  G03B17/561

Abstract: A retractable post with an alarm device includes a plurality of retractable pipes retractably sleeved with each other. A retractable air whistle is secured by a latch block at a proper location inside the retractable pipe. A plug piece is installed at a bottom of the retractable post. The plug piece and the latch block make an interior of the retractable pipe present a dummy seal state, wherein the retractable pipe is almost but not completely sealed. When an abnormal rapid falling displacement of the retractable pipes occurs, the latch block and the retractable air whistle compress the air inside the retractable pipe, and then a bellow of the retractable air whistle is further compressed, such that the air inside the bellow is rapidly discharged through a sounding valve disposed at a front end of the air whistle, thereby generating an alarm sound.

Abstract translation: 具有报警装置的可伸缩柱包括多个可伸缩地套管的伸缩管。 可收缩的空气哨子由可收缩管内的适当位置处的闩锁块固定。 插头片安装在可伸缩柱的底部。 插头片和闩锁块使可伸缩管的内部呈现虚拟密封状态，其中可伸缩管几乎而不完全密封。 当发生可伸缩管的异常快速下降移动时，闩锁块和可伸缩空气口哨压缩可伸缩管内的空气，然后可伸缩空气哨子的波纹管被进一步压缩，使得波纹管内部的空气迅速 通过设置在空气哨子的前端的探测阀排出，从而产生报警声。

公开(公告)号：US20130095616A1

公开(公告)日：2013-04-18

申请号：US13275337

申请日：2011-10-18

Applicant: Shih-Hung Tsai ,  Chien-Liang Lin ,  Chien-Ting Lin ,  Ssu-I Fu ,  Ying-Tsung Chen

Inventor： Shih-Hung Tsai ,  Chien-Liang Lin ,  Chien-Ting Lin ,  Ssu-I Fu ,  Ying-Tsung Chen

IPC: H01L21/336

CPC classification number: H01L29/66795

Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.

Abstract translation: 一种制造多栅极晶体管器件的方法包括：提供具有图案化半导体层，栅极电介质层和顺序地形成在其上的栅极层的半导体衬底，形成依次具有第一绝缘层和第二绝缘层的覆盖层 图案化半导体层和栅极层，去除多个绝缘层的一部分以同时在栅极层周围形成第一间隔物，以及围绕图案化半导体层形成第二间隔物，去除第二间隔物以暴露第一绝缘层的一部分 覆盖图案化的半导体层并且同时移除第一间隔物的一部分以形成围绕栅极层的第三间隔物，以及去除暴露的第一绝缘层以暴露图案化的半导体层。

公开(公告)号：US08404535B2

公开(公告)日：2013-03-26

申请号：US13304409

申请日：2011-11-25

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L21/28

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 首先，提供具有第一晶体管区域和第二晶体管区域的衬底。 接下来，在基板上形成层叠膜，其中层叠膜包括至少一个高k电介质层和第一金属层。 图案化层叠的膜以在第一晶体管区域和第二晶体管区域中形成多个栅极，在栅极上形成电介质层，并且介电层的一部分被平坦化，直到到达每个栅极的顶部。 第一金属层从第二晶体管区域的栅极去除，并且第二金属层形成在电介质层的表面上，每个栅极用于在第一晶体管区域和第二晶体管区域中形成多个金属栅极。

公开(公告)号：US20120256276A1

公开(公告)日：2012-10-11

申请号：US13082387

申请日：2011-04-07

Applicant: Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

Inventor： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Abstract translation: 提供一种制造金属栅极的方法。 该方法包括提供基板。 然后，在基板上形成栅极电介质层。 在栅极电介质层上形成具有功函数金属层的多层堆叠结构。 在多层堆叠结构的至少一层上进行O2气氛处理。 在多层堆叠结构上形成导电层。