公开(公告)号：US20120045880A1

公开(公告)日：2012-02-23

申请号：US12860939

申请日：2010-08-23

Applicant: Cheng-Yu Ma ,  Wen-Han Hung ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Tzyy-Ming Cheng

Inventor： Cheng-Yu Ma ,  Wen-Han Hung ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供衬底，其中衬底包括限定在其上的晶体管区域; 在所述基板上形成栅极绝缘层; 在所述栅绝缘层上形成层叠膜，其中所述层叠膜包括至少一个蚀刻停止层，多晶硅层和硬掩模; 图案化栅极绝缘层和用于在基板上形成伪栅极的叠层膜; 在所述虚拟栅极上形成介电层; 执行用于部分去除电介质层直到到达虚拟栅极的顶部的平坦化处理; 去除虚拟栅极的多晶硅层; 去除用于形成开口的虚拟栅极的蚀刻停止层; 以及在用于形成栅极的开口中形成导电层。

公开(公告)号：US20120256276A1

公开(公告)日：2012-10-11

申请号：US13082387

申请日：2011-04-07

Applicant: Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

Inventor： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Abstract translation: 提供一种制造金属栅极的方法。 该方法包括提供基板。 然后，在基板上形成栅极电介质层。 在栅极电介质层上形成具有功函数金属层的多层堆叠结构。 在多层堆叠结构的至少一层上进行O2气氛处理。 在多层堆叠结构上形成导电层。

公开(公告)号：US09384962B2

公开(公告)日：2016-07-05

申请号：US13082387

申请日：2011-04-07

Applicant: Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

Inventor： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC: H01L21/28 ,  H01L21/02

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Abstract translation: 提供一种制造金属栅极的方法。 该方法包括提供基板。 然后，在基板上形成栅极电介质层。 在栅极电介质层上形成具有功函数金属层的多层堆叠结构。 在多层堆叠结构的至少一层上进行O2气氛处理。 在多层堆叠结构上形成导电层。

公开(公告)号：US20120319214A1

公开(公告)日：2012-12-20

申请号：US13161512

申请日：2011-06-16

Applicant: Cheng-Yu Ma ,  Wen-Han Hung

Inventor： Cheng-Yu Ma ,  Wen-Han Hung

IPC: H01L21/3205 ,  H01L29/78

CPC classification number: H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating a metal gate includes the following steps. First, a substrate having an interfacial dielectric layer above the substrate is provided. Then, a gate trench having a barrier layer is formed in the interfacial dielectric layer. A source layer is disposed above the barrier layer. Next, a process is performed to have at least one element in the source layer move into the barrier layer. Finally, the barrier layer is removed and a metal layer fills up the gate trench.

Abstract translation: 一种制造金属栅极的方法包括以下步骤。 首先，提供在基板上方具有界面电介质层的基板。 然后，在界面电介质层中形成具有阻挡层的栅极沟槽。 源层设置在阻挡层上方。 接下来，执行处理以使源层中的至少一个元素移动到阻挡层中。 最后，去除阻挡层，并且金属层填满栅极沟槽。

公开(公告)号：US08211775B1

公开(公告)日：2012-07-03

申请号：US13043479

申请日：2011-03-09

Applicant: Cheng-Yu Ma ,  Wen-Han Hung ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Tzyy-Ming Cheng

Inventor： Cheng-Yu Ma ,  Wen-Han Hung ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L29/66553 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/6656

Abstract: A method for forming a transistor having a metal gate is provided. A substrate is provided first. A transistor is formed on the substrate. The transistor includes a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on the high-k gate dielectric layer, and a dummy gate disposed on the oxygen containing dielectric layer. Then, the dummy gate and the patterned gate dielectric layer are removed. Lastly, a metal gate is formed and the metal gate directly contacts the high-k gate oxide.

Abstract translation: 提供一种形成具有金属栅极的晶体管的方法。 首先提供基板。 在基板上形成晶体管。 晶体管包括高k栅极电介质层，设置在高k栅极电介质层上的含氧电介质层和设置在含氧电介质层上的伪栅极。 然后，去除伪栅极和图案化栅极电介质层。 最后，形成金属栅极，并且金属栅极直接接触高k栅极氧化物。

公开(公告)号：US6044332A

公开(公告)日：2000-03-28

申请号：US60841

申请日：1998-04-15

Applicant: Kofi Korsah ,  William B. Dress ,  Cheng Yu Ma ,  Michael R. Moore

Inventor： Kofi Korsah ,  William B. Dress ,  Cheng Yu Ma ,  Michael R. Moore

IPC: G01N29/02 ,  G01N29/24 ,  G01N29/46 ,  G01N30/00 ,  G01R23/167

CPC classification number: G01N29/2462 ,  G01N29/022 ,  G01N29/2468 ,  G01N29/46 ,  G01N2291/014 ,  G01N2291/0212 ,  G01N2291/0256 ,  G01N2291/0423

Abstract: A method for sensing and analyzing data with surface acoustic wave (SAW) devices comprises the steps of: propagating a sampling signal at a fundamental frequency through a SAW device coated for selective adsorption; measuring at least one parameter of at least one higher order harmonic of the fundamental frequency sampling signal; exposing the coated SAW device to enable the selective adsorption; measuring the at least one parameter of the at least one higher order harmonic of the fundamental frequency sampling signal after the exposing step; comparing the measurements of the at least one parameter of the at least one higher order harmonic before and after the exposing step; and, deriving a result of the selective adsorption based upon the comparing step. The at least one parameter is harmonic power and harmonic frequency. The at least one higher order harmonic is one or more odd harmonics.

Abstract translation: 一种用表面声波（SAW）器件检测和分析数据的方法包括以下步骤：通过涂覆选择性吸附的SAW器件以基频传播采样信号; 测量所述基频采样信号的至少一个高次谐波的至少一个参数; 暴露涂覆的SAW器件以实现选择性吸附; 在所述曝光步骤之后，测量所述基频采样信号的所述至少一个高次谐波的至少一个参数; 比较所述暴露步骤之前和之后所述至少一个较高阶谐波的所述至少一个参数的测量值; 并且基于比较步骤得到选择性吸附的结果。 至少一个参数是谐波功率和谐波频率。 至少一个高阶谐波是一个或多个奇次谐波。

公开(公告)号：US08673758B2

公开(公告)日：2014-03-18

申请号：US13161512

申请日：2011-06-16

Applicant: Cheng-Yu Ma ,  Wen-Han Hung

Inventor： Cheng-Yu Ma ,  Wen-Han Hung

IPC: H01L21/3205 ,  H01L29/78

CPC classification number: H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating a metal gate includes the following steps. First, a substrate having an interfacial dielectric layer above the substrate is provided. Then, a gate trench having a barrier layer is formed in the interfacial dielectric layer. A source layer is disposed above the barrier layer. Next, a process is performed to have at least one element in the source layer move into the barrier layer. Finally, the source layer is removed and a metal layer fills up the gate trench.

Abstract translation: 一种制造金属栅极的方法包括以下步骤。 首先，提供在基板上方具有界面电介质层的基板。 然后，在界面电介质层中形成具有阻挡层的栅极沟槽。 源层设置在阻挡层上方。 接下来，执行处理以使源层中的至少一个元素移动到阻挡层中。 最后，去除源极层，并且金属层填满栅极沟槽。

公开(公告)号：US08404533B2

公开(公告)日：2013-03-26

申请号：US12860939

申请日：2010-08-23

Applicant: Cheng-Yu Ma ,  Wen-Han Hung ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Tzyy-Ming Cheng

Inventor： Cheng-Yu Ma ,  Wen-Han Hung ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Tzyy-Ming Cheng

IPC: H01L21/338

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供衬底，其中衬底包括限定在其上的晶体管区域; 在所述基板上形成栅极绝缘层; 在所述栅绝缘层上形成层叠膜，其中所述层叠膜包括至少一个蚀刻停止层，多晶硅层和硬掩模; 图案化栅极绝缘层和用于在基板上形成伪栅极的叠层膜; 在所述虚拟栅极上形成介电层; 执行用于部分去除电介质层直到到达虚拟栅极的顶部的平坦化处理; 去除虚拟栅极的多晶硅层; 去除用于形成开口的虚拟栅极的蚀刻停止层; 以及在用于形成栅极的开口中形成导电层。