公开(公告)号：US07160780B2

公开(公告)日：2007-01-09

申请号：US11066703

申请日：2005-02-23

Applicant: Chul Lee ,  Jae-Man Yoon ,  Choong-Ho Lee

Inventor： Chul Lee ,  Jae-Man Yoon ,  Choong-Ho Lee

IPC: H01L21/336

CPC classification number: H01L29/7851 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795

Abstract: In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of the fin active region, along a line shape that at least one time crosses with the fin active region, thus forming a trench. The fin active region is exposed by the trench and thereon a gate insulation layer is formed. Thereby, productivity is increased and performance of the device is improved. A fin FET employs a bulk silicon substrate of which a manufacturing cost is lower than that of a conventional SOI type silicon substrate. Also, a floating body effect can be prevented, or is substantially reduced.

Abstract translation: 在一个示例性实施例中，翅片有源区域沿着整体形成浅沟槽绝缘体的体硅基板沿着一个方向突出，以覆盖翅片有源区域。 去除浅沟槽绝缘体，以沿着至少一次与翅片有源区交叉的线形状选择性地暴露翅片有源区的上部和侧壁，从而形成沟槽。 翅片有源区域被沟槽暴露，并且形成有栅极绝缘层。 从而，提高了生产效率并提高了设备​​的性能。 翅片FET采用其制造成本低于常规SOI型硅衬底的制造成本的体硅衬底。 此外，可以防止浮体效应或大大降低浮体效应。

公开(公告)号：US20050269629A1

公开(公告)日：2005-12-08

申请号：US11084922

申请日：2005-03-21

Applicant: Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

Inventor： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L21/26513 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/78624

Abstract: A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

Abstract translation: 翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。 翅片在基底上并沿着和垂直方向横向延伸。 栅电极覆盖翅片的一侧和顶部。 栅绝缘层位于栅电极和鳍之间。 翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。 翅片的源极区域具有与鳍片的漏极区域不同的宽度。

公开(公告)号：US20050267317A1

公开(公告)日：2005-12-01

申请号：US11016293

申请日：2004-12-17

Applicant: Tae-Ho Yoon ,  Chul Lee ,  Kwak Min

Inventor： Tae-Ho Yoon ,  Chul Lee ,  Kwak Min

IPC: C07B61/00 ,  C07F9/02 ,  C07F9/53 ,  C07F9/553 ,  C08G73/10

CPC classification number: C08G73/0246 ,  C07F9/5325 ,  C07F9/5537

Abstract: The present invention relates to bisphenyl-2,3,5,6-tetrafluoro-4-trifluoromethylphenylphosphine oxide compounds and synthesis thereof, more particularly to novel bisphenyl-2,3,5,6-tetrafluoro-4-trifluoromethylphenylphosphine oxide compounds having both a perfluorinated benzene substituent and a phosphine oxide moiety. Compounds of the invention can be useful as a monomer for preparing polyimides having a low dielectric constant and a superior adhesion while maintaining the superior thermal and mechanical properties of polyimides themselves, and their synthesis thereof.

Abstract translation: 本发明涉及双苯基-2,3,5,6-四氟-4-三氟甲基苯基氧化膦化合物及其合成，更具体地涉及新的双苯基-2,3,5,6-四氟-4-三氟甲基苯基氧化膦化合物，其具有 全氟化苯取代基和氧化膦部分。 本发明的化合物可用作制备具有低介电常数和优异粘附性的聚酰亚胺的单体，同时保持聚酰亚胺本身的优异的热和机械性能及其合成。

公开(公告)号：US20050250285A1

公开(公告)日：2005-11-10

申请号：US11091457

申请日：2005-03-28

Applicant: Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

Inventor： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L29/7851 ,  H01L21/84 ,  H01L29/66795

Abstract: Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

Abstract translation: 形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。 鳍形半导体有源区域的至少上部被牺牲层覆盖。 该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。 电绝缘区域形成在牺牲间隔物上。 然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。 然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

公开(公告)号：US20050088585A1

公开(公告)日：2005-04-28

申请号：US10972449

申请日：2004-10-26

Applicant: Chul Lee

Inventor： Chul Lee

IPC: G02F1/13357 ,  G02F1/133 ,  G02F1/1335 ,  H01L35/30

CPC classification number: H01L35/30 ,  G02F1/133

Abstract: A liquid crystal display device includes a backlight unit having a lamp, wherein the lamp includes opposing ends and electrodes at respective ones of the opposing ends; at least one thermoelectric device operably proximate to the lamp; and a liquid crystal (LC) panel over the backlight unit. Each thermoelectric device includes a hot junction disposed near the lamp; a cold junction spaced apart from the hot junction and disposed farther from the lamp than the hot junction; two different thermoelectric materials between the hot and cold junctions, wherein the two different thermoelectric materials are spaced from each other and wherein opposing ends of each of the different thermoelectric materials contact the hot and cold junctions; and first and second wires connected to respective ones of the two different thermoelectric materials.

Abstract translation: 液晶显示装置包括具有灯的背光单元，其中所述灯在相对端的相应端部包括相对端和电极; 至少一个可操作地靠近所述灯的热电装置; 以及背光单元上的液晶（LC）面板。 每个热电装置包括设置在灯附近的热连接点; 与热接点间隔开的冷连接处，并且比热连接处设置得比灯更远; 两个不同的热电材料在热连接点和冷连接点之间，其中两个不同的热电材料彼此间隔开，并且每个不同热电材料的相对端部接触热连接点和冷连接点; 以及连接到两个不同热电材料中的相应的第一和第二导线。

公开(公告)号：US20050055714A1

公开(公告)日：2005-03-10

申请号：US10897951

申请日：2004-07-22

Applicant: Chul Lee

Inventor： Chul Lee

IPC: H04H20/00 ,  H04H20/28 ,  H04H20/33 ,  H04H20/86 ,  H04H20/95 ,  H04N5/44 ,  H04N7/08 ,  H04N7/081 ,  H04N7/12 ,  H04J11/00 ,  G06F3/00 ,  G06F13/00 ,  H04N5/445

CPC classification number: H04H40/27 ,  H04H20/28 ,  H04H20/46 ,  H04H20/72 ,  H04H20/86 ,  H04H60/13 ,  H04H2201/20

Abstract: The present invention provides an apparatus for transmitting/receiving information for digital multimedia broadcast (DMB) service and method thereof, by which data required for decoding is transmitted fast and by which the received data is facilitated to be quickly decoded. The present invention includes coding a service information including at least one of a simplified PAT (program association table), a modified PMT (program map table), a modified IOD (initial object descriptor), and an ES (elementary stream) descriptor into a FIC (fast information channel) structure and performing interleaving and error correction on an audio/video signal to code into an MSC (main service channel) structure, multiplexing the FIC-coded service information, the MSC-coded audio/video signal, and data, modulating the multiplexed signal, and converting the modulated signal to an RF (radio frequency) band signal to transmit.

Abstract translation: 本发明提供了一种用于数字多媒体广播（DMB）业务的信息发送/接收的装置及其方法，由此快速传送解码所需的数据，便于快速解码所接收的数据。 本发明包括将包括简化PAT（程序关联表），修改的PMT（程序映射表），修改的IOD（初始对象描述符）和ES（基本流））描述符中的至少一个的服务信息编码为 FIC（快速信息通道）结构，并且对音频/视频信号进行交织和纠错以编码到MSC（主服务信道）结构中，对FIC编码的服务信息，MSC编码的音频/视频信号和数据进行复用 调制多路复用信号，并将调制信号转换成RF（射频）频带信号进行发送。

公开(公告)号：US20120273791A1

公开(公告)日：2012-11-01

申请号：US13546296

申请日：2012-07-11

Applicant: Bongsoo Kim ,  Chul Lee ,  Deoksung Hwang ,  Sang-Bin Ahn

Inventor： Bongsoo Kim ,  Chul Lee ,  Deoksung Hwang ,  Sang-Bin Ahn

IPC: H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/823437 ,  H01L29/66621 ,  H01L29/78

Abstract: A polycrystalline semiconductor layer is formed on a cell active region and a peripheral active region of a substrate. A buried gate electrode is formed in the substrate in the cell active region at a level below the polycrystalline semiconductor layer after forming the polycrystalline semiconductor layer. A gate electrode is formed on the substrate in the peripheral active region from the polysilicon semiconductor layer after forming the buried gate electrode.

Abstract translation: 多晶半导体层形成在基板的单元有源区和周边有源区上。 在形成多晶半导体层之后，在多晶半导体层下方的电池有源区的基板中形成埋入栅电极。 在形成掩埋栅电极之后，在多晶硅半导体层的外围有源区的基板上形成栅电极。

公开(公告)号：USD637573S1

公开(公告)日：2011-05-10

申请号：US29378286

申请日：2010-11-02

Applicant: Chul Lee ,  Myung Whoon Lee ,  Jong Chul Kim

Designer： Chul Lee ,  Myung Whoon Lee ,  Jong Chul Kim

公开(公告)号：USD606504S1

公开(公告)日：2009-12-22

申请号：US29271377

申请日：2007-01-18

Applicant: Chul Lee

Designer： Chul Lee

公开(公告)号：US07531412B2

公开(公告)日：2009-05-12

申请号：US11151673

申请日：2005-06-13

Applicant: Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

Inventor： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

IPC: H01L21/336

CPC classification number: H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

Abstract: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

Abstract translation: 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。