公开(公告)号：US07323375B2

公开(公告)日：2008-01-29

申请号：US11091457

申请日：2005-03-28

申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

IPC分类号： H01L21/00

CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L29/66795

摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

摘要翻译： 形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。 鳍形半导体有源区域的至少上部被牺牲层覆盖。 该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。 电绝缘区域形成在牺牲间隔物上。 然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。 然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

公开(公告)号：US07160780B2

公开(公告)日：2007-01-09

申请号：US11066703

申请日：2005-02-23

申请人： Chul Lee ,  Jae-Man Yoon ,  Choong-Ho Lee

发明人： Chul Lee ,  Jae-Man Yoon ,  Choong-Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7851 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795

摘要： In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of the fin active region, along a line shape that at least one time crosses with the fin active region, thus forming a trench. The fin active region is exposed by the trench and thereon a gate insulation layer is formed. Thereby, productivity is increased and performance of the device is improved. A fin FET employs a bulk silicon substrate of which a manufacturing cost is lower than that of a conventional SOI type silicon substrate. Also, a floating body effect can be prevented, or is substantially reduced.

摘要翻译： 在一个示例性实施例中，翅片有源区域沿着整体形成浅沟槽绝缘体的体硅基板沿着一个方向突出，以覆盖翅片有源区域。 去除浅沟槽绝缘体，以沿着至少一次与翅片有源区交叉的线形状选择性地暴露翅片有源区的上部和侧壁，从而形成沟槽。 翅片有源区域被沟槽暴露，并且形成有栅极绝缘层。 从而，提高了生产效率并提高了设备​​的性能。 翅片FET采用其制造成本低于常规SOI型硅衬底的制造成本的体硅衬底。 此外，可以防止浮体效应或大大降低浮体效应。

公开(公告)号：US20050269629A1

公开(公告)日：2005-12-08

申请号：US11084922

申请日：2005-03-21

申请人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

发明人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L21/26513 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/78624

摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

摘要翻译： 翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。 翅片在基底上并沿着和垂直方向横向延伸。 栅电极覆盖翅片的一侧和顶部。 栅绝缘层位于栅电极和鳍之间。 翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。 翅片的源极区域具有与鳍片的漏极区域不同的宽度。

公开(公告)号：US20050250285A1

公开(公告)日：2005-11-10

申请号：US11091457

申请日：2005-03-28

申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/786 ,  H01L29/94

CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L29/66795

摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

摘要翻译： 形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。 鳍形半导体有源区域的至少上部被牺牲层覆盖。 该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。 电绝缘区域形成在牺牲间隔物上。 然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。 然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

公开(公告)号：US07883972B2

公开(公告)日：2011-02-08

申请号：US12219984

申请日：2008-07-31

申请人： Jae-Man Yoon ,  Choong-Ho Lee ,  Chul Lee ,  Dong-Gun Park

发明人： Jae-Man Yoon ,  Choong-Ho Lee ,  Chul Lee ,  Dong-Gun Park

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795

摘要： A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

摘要翻译： 半导体器件可以包括具有连接在源极/漏极图案之间的源极/漏极区域和沟道鳍片的鳍结构。 栅极绝缘层可以设置在通道散热片上。 栅电极可以包括下栅极图案和上栅极图案。 下栅极图案可以在垂直方向上延伸并接触栅极绝缘层。 上栅极图案可以在基本上垂直于第一水平方向的第二水平方向上延伸。 上栅极图案可以连接到下栅极图案的上部。

公开(公告)号：US07521766B2

公开(公告)日：2009-04-21

申请号：US11070598

申请日：2005-03-01

申请人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

发明人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

摘要翻译： 根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。 活性结构包括在源极/漏极区域下形成阻挡区的沟槽。 栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。 可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

公开(公告)号：US07407845B2

公开(公告)日：2008-08-05

申请号：US11048369

申请日：2005-01-31

申请人： Choong-Ho Lee ,  Jae-Man Yoon ,  Dong-Gun Park ,  Chul Lee

发明人： Choong-Ho Lee ,  Jae-Man Yoon ,  Dong-Gun Park ,  Chul Lee

IPC分类号： H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/78603 ,  H01L29/78648

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.

摘要翻译： 在一个实施例中，半导体器件包括具有下层和覆盖在下层上的上层的半导体衬底。 上层被布置和构造成形成彼此间隔开并从下层的上表面突出的第一和第二有源区。 桥接形状的第三有源区域与下层的上表面垂直地间隔开并且连接第一和第二有源区域。 该器件还包括栅电极，其形成有围绕第三有源区的栅绝缘层，使得第三有源区用作沟道。

公开(公告)号：US20060097304A1

公开(公告)日：2006-05-11

申请号：US11151673

申请日：2005-06-13

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。

公开(公告)号：US20060017104A1

公开(公告)日：2006-01-26

申请号：US11183997

申请日：2005-07-19

申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/78696 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/78642

摘要： A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel pattern. A gate electrode may be provided on the gate insulation layer. The gate electrode may fill the channel pattern. A conductive region, which may serve as lower source/drain regions, may be formed at a surface portion of the semiconductor substrate. The conductive region may contact a lower portion of the channel pattern. A conductive pattern, which may serve as upper source/drain regions, may horizontally extend from an upper portion of the channel pattern.

公开(公告)号：US07531412B2

公开(公告)日：2009-05-12

申请号：US11151673

申请日：2005-06-13

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。