公开(公告)号：US20100267210A1

公开(公告)日：2010-10-21

申请号：US12662393

申请日：2010-04-14

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/8239

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US20070080385A1

公开(公告)日：2007-04-12

申请号：US11450936

申请日：2006-06-09

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L29/94

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US08053307B2

公开(公告)日：2011-11-08

申请号：US12662393

申请日：2010-04-14

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US07728373B2

公开(公告)日：2010-06-01

申请号：US11705109

申请日：2007-02-12

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/2842

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US20070284647A1

公开(公告)日：2007-12-13

申请号：US11705109

申请日：2007-02-12

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US20130187291A1

公开(公告)日：2013-07-25

申请号：US13789028

申请日：2013-03-07

申请人： Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

发明人： Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively.

摘要翻译： 集成电路器件包括在其中具有多个沟槽隔离区域的半导体衬底，其中限定了它们之间的相应的半导体有源区。 沟槽设置在半导体衬底中。 沟槽具有分别限定与第一沟槽隔离区域和第一有源区域相对的界面的第一和第二相对的侧壁。 第一电互连设置在沟槽的底部。 提供了一种电绝缘覆盖图案，其在第一电互连和沟槽的顶部之间延伸。 还提供了互连绝缘层，其将沟槽的第一和第二侧壁和底部排列。 互连绝缘层在第一电互连和第一有源区之间延伸。 在第一活动区域设置有凹部。 凹部具有限定与互连绝缘层的界面的侧壁。 还提供了第二电互连，其延伸在：（i）第一沟槽隔离区的上表面，（ii）电绝缘封盖图案; 和（iii）凹槽的侧壁。 第一和第二电互连分别在第一和第二正交方向跨越半导体衬底延伸。

公开(公告)号：US20110175229A1

公开(公告)日：2011-07-21

申请号：US12944876

申请日：2010-11-12

申请人： Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

发明人： Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

IPC分类号： H01L23/522

CPC分类号： H01L23/481 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively.

摘要翻译： 集成电路器件包括在其中具有多个沟槽隔离区域的半导体衬底，其中限定了它们之间的相应的半导体有源区。 沟槽设置在半导体衬底中。 沟槽具有分别限定与第一沟槽隔离区域和第一有源区域相对的界面的第一和第二相对的侧壁。 第一电互连设置在沟槽的底部。 提供了一种电绝缘覆盖图案，其在第一电互连和沟槽的顶部之间延伸。 还提供了互连绝缘层，其将沟槽的第一和第二侧壁和底部排列。 互连绝缘层在第一电互连和第一有源区之间延伸。 在第一活动区域设置有凹部。 凹部具有限定与互连绝缘层的界面的侧壁。 还提供了第二电互连，其延伸在：（i）第一沟槽隔离区的上表面，（ii）电绝缘封盖图案; 和（iii）凹槽的侧壁。 第一和第二电互连分别在第一和第二正交方向跨越半导体衬底延伸。

公开(公告)号：US20100272092A1

公开(公告)日：2010-10-28

申请号：US12745747

申请日：2008-07-09

申请人： Hoon Jeong ,  Jong-Oh Lee ,  Bong-Soo Kim ,  Jong-Suk Chae

发明人： Hoon Jeong ,  Jong-Oh Lee ,  Bong-Soo Kim ,  Jong-Suk Chae

IPC分类号： H04W72/04

CPC分类号： H04W72/005 ,  H04W52/0216 ,  H04W52/0219 ,  H04W72/1268 ,  H04W72/1289 ,  H04W84/18 ,  Y02D70/00 ,  Y02D70/144 ,  Y02D70/166

摘要： Provided are an apparatus and method for broadcasting data, and an apparatus and method for broadcasting response data, of a sensor node in a beacon mode in a wireless sensor network system including a plurality of nodes. According to the apparatus and method for broadcasting data, an admission application message requesting an admission of a sensor node is transmitted to the wireless sensor network system, in which time-division time slots are assigned to each of the nodes of the wireless sensor network system, wherein, in the time-division time slot, the reception function of the node is activated and sensing data is transmitted; a beacon frame is received, which includes information that indicates a broadcasting time slot among the time-division time slots, wherein, in the broadcasting time slot, the reception function of each of the nodes of the wireless sensor network system having received the admission application message, is activated at the same time; and broadcasting data is transmitted during the broadcasting time slot. Accordingly, broadcasting data can be efficiently transmitted in a beacon mode of the wireless sensor network system.

摘要翻译： 提供了一种用于在包括多个节点的无线传感器网络系统中以信标模式广播数据的装置和方法以及用于广播响应数据的装置和方法。 根据用于广播数据的装置和方法，向无线传感器网络系统发送请求许可传感器节点的准入申请消息，其中分配时隙被分配给无线传感器网络系统的每个节点 其中，在时分时隙中，节点的接收功能被激活并且发送感测数据; 接收到信标帧，其包括指示时分时隙之间的广播时隙的信息，其中在广播时隙中，已经接收到准入应用的无线传感器网络系统的每个节点的接收功能 消息，同时激活; 并且在广播时隙期间发送广播数据。 因此，能够以无线传感器网络系统的信标模式有效地发送广播数据。

公开(公告)号：US07772103B2

公开(公告)日：2010-08-10

申请号：US12146729

申请日：2008-06-26

申请人： Ho-Jun Yi ,  Yong-Il Kim ,  Bong-Soo Kim ,  Dae-Young Jang ,  Woo-Jeong Cho

发明人： Ho-Jun Yi ,  Yong-Il Kim ,  Bong-Soo Kim ,  Dae-Young Jang ,  Woo-Jeong Cho

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/105 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of forming a wire structure, first active regions and second active regions are formed on a substrate. Each of the first active regions has a first sidewall of a positive slope and a second sidewall opposed to the first sidewall. The second active regions are arranged along a first direction. An isolation layer is between the first active regions and the second active regions. A first mask is formed on the first active regions, the second active regions and the isolation layer. The first mask has an opening exposing the first sidewall and extending along the first direction. The first active regions, the second active regions and the isolation layer are etched using the first mask to form a groove extending along the first direction and to form a fence having a height substantially higher than a bottom face of the groove. A wire is formed to fill the groove. A contact is formed on the wire. The contact is disposed toward the second active regions from the fence.

摘要翻译： 在形成线结构的方法中，在衬底上形成第一有源区和第二有源区。 每个第一有源区具有正斜率的第一侧壁和与第一侧壁相对的第二侧壁。 第二有源区沿第一方向排列。 隔离层位于第一有源区和第二有源区之间。 第一掩模形成在第一有源区，第二有源区和隔离层上。 第一掩模具有暴露第一侧壁并沿着第一方向延伸的开口。 使用第一掩模蚀刻第一有源区，第二有源区和隔离层，以形成沿着第一方向延伸的凹槽，并形成具有高于凹槽的底面的高度的栅栏。 形成线以填充凹槽。 在导线上形成接触。 接触件从栅栏朝向第二活动区域设置。

公开(公告)号：US20080061382A1

公开(公告)日：2008-03-13

申请号：US11704364

申请日：2007-02-09

申请人： Seong-Goo Kim ,  Kang-Yoon Lee ,  Yun-Gi Kim ,  Bong-Soo Kim

发明人： Seong-Goo Kim ,  Kang-Yoon Lee ,  Yun-Gi Kim ,  Bong-Soo Kim

IPC分类号： H01L29/768 ,  H01L21/336 ,  H01L21/4763 ,  H01L23/52

CPC分类号： H01L23/485 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

摘要翻译： 提供晶体管，半导体集成电路互连及其形成方法。 晶体管，半导体集成电路互连及其形成方法可以改善栅电极或互连电极之间的电特性，并简化与栅电极或互连电极相关的半导体制造工艺。 可以制备具有第一和第二区域的材料层。 可以在第一区域的选定部分中形成沟槽。 晶体管或半导体集成电路互连可以分别在第一和第二区域中。 晶体管之一或半导体集成电路互连可以形成在沟槽中。 晶体管或半导体集成电路互连可以彼此电绝缘。