公开(公告)号：US07781285B2

公开(公告)日：2010-08-24

申请号：US11450936

申请日：2006-06-09

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US20100283094A1

公开(公告)日：2010-11-11

申请号：US12840599

申请日：2010-07-21

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US08174065B2

公开(公告)日：2012-05-08

申请号：US12840599

申请日：2010-07-21

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L29/66

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US20070080385A1

公开(公告)日：2007-04-12

申请号：US11450936

申请日：2006-06-09

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L29/94

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US08053307B2

公开(公告)日：2011-11-08

申请号：US12662393

申请日：2010-04-14

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US07728373B2

公开(公告)日：2010-06-01

申请号：US11705109

申请日：2007-02-12

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/2842

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US20070284647A1

公开(公告)日：2007-12-13

申请号：US11705109

申请日：2007-02-12

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US20100267210A1

公开(公告)日：2010-10-21

申请号：US12662393

申请日：2010-04-14

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/8239

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US07659597B2

公开(公告)日：2010-02-09

申请号：US11675829

申请日：2007-02-16

申请人： Seong-Goo Kim ,  Yun-Gi Kim ,  Jae-Man Yoon ,  Hyeoung-Won Seo

发明人： Seong-Goo Kim ,  Yun-Gi Kim ,  Jae-Man Yoon ,  Hyeoung-Won Seo

IPC分类号： H01L23/52 ,  H01L21/336

CPC分类号： H01L29/4236 ,  H01L21/28123 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/52 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.

摘要翻译： 集成电路器件包括其中包括沟槽的衬底和沟槽中的导电插头线图案。 导电插头线图案包括露出沟槽的相对侧壁的部分的凹陷部分和从凹陷部分的表面突出的整体插塞部分，以提供与不同层级上的至少一个其它导电线图案的电连接 的金属化。 插塞部分的表面可以突出到与沟槽相邻并且在沟槽外部的衬底的表面基本相同的水平面，并且凹部的表面可以在沟槽外部的衬底的表面下方。 还讨论了相关的制造方法。

公开(公告)号：US20080067697A1

公开(公告)日：2008-03-20

申请号：US11675829

申请日：2007-02-16

申请人： Seong-Goo Kim ,  Yung-Gi Kim ,  Jae-Man Yoon ,  Hyeoung-Won Seo

发明人： Seong-Goo Kim ,  Yung-Gi Kim ,  Jae-Man Yoon ,  Hyeoung-Won Seo

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L29/4236 ,  H01L21/28123 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/52 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.

摘要翻译： 集成电路器件包括其中包括沟槽的衬底和沟槽中的导电插头线图案。 导电插头线图案包括露出沟槽的相对侧壁的部分的凹陷部分和从凹陷部分的表面突出的整体插塞部分，以提供与不同层级上的至少一个其它导电线图案的电连接 的金属化。 插塞部分的表面可以突出到与沟槽相邻并且在沟槽外部的衬底的表面基本相同的水平面，并且凹部的表面可以在沟槽外部的衬底的表面下方。 还讨论了相关的制造方法。