公开(公告)号：US20080028700A1

公开(公告)日：2008-02-07

申请号：US11496621

申请日：2006-08-01

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: E04B7/18

CPC classification number: E04D3/08 ,  A01G9/16 ,  E04D2003/0806 ,  E04D2003/085 ,  Y02A40/254

Abstract: The invention relates to an assembled greenhouse structure, mainly comprised of a frame structure and a transparent or translucent sheet material that is disposed on the frame; the characteristic of the invention lies in that the frame for positioning said sheet material is composed of a stand, roof sheathing, and connectors; the stand and the roof sheathing are formed as aluminum alloy extrusions, the connectors are an elastic member, having one end thereof embedded in a sliding slot on the inner side of the roof sheathing, and the other end thereof has an elastic hook portion vertically inserted in a slot coupling corresponding to the stand. Accordingly, the invention disclosed herein achieves the objectives of presenting a pleasant appearance from the exterior and with the advantage of rapid assembly of the greenhouse.

Abstract translation: 本发明涉及一种组装的温室结构，主要由框架结构和布置在框架上的透明或半透明板材构成; 本发明的特征在于用于定位所述片材的框架由支架，屋顶护套和连接器组成; 支架和屋顶护套形成为铝合金挤压件，连接器是弹性件，其一端嵌入屋顶护套内侧的滑动槽中，另一端具有垂直插入的弹性钩部 在与支架相对应的狭槽联接中。 因此，本文公开的发明实现了从外部呈现愉悦的外观并且具有快速组装温室的优点的目的。

公开(公告)号：US20070024251A1

公开(公告)日：2007-02-01

申请号：US11242915

申请日：2005-10-05

Applicant: Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

Inventor： Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

IPC: G05F1/00

CPC classification number: G05F1/70

Abstract: The continuous conduction mode (CCM) boost voltage power factor correction apparatus with an average-current control mode of the present invention uses resettable integrators to integrate the difference voltage signal outputted from the voltage error amplifier and the input current signal obtained from detection. The integration results are then compared to control the duty cycle of the switch. Thereby, the input current and the input voltage in the AC/DC electrical power converter have a proportion relation and their phases are the same as each other. The components used in this control method are simpler than the PFC circuit of the prior art. It is easy to integrate in one chip with fewer pins. The apparatus of the present invention has a high power factor and a low total harmonic distortion (THD).

Abstract translation: 具有本发明的平均电流控制模式的连续导通模式（CCM）升压电压功率因数校正装置使用可复位积分器来积分从电压误差放大器输出的差分电压信号和从检测获得的输入电流信号。 然后将积分结果进行比较，以控制开关的占空比。 因此，AC / DC电力转换器的输入电流和输入电压具有比例关系，它们的相位彼此相同。 在该控制方法中使用的部件比现有技术的PFC电路简单。 在一个芯片中集成更少的引脚很容易。 本发明的装置具有高功率因数和低总谐波失真（THD）。

公开(公告)号：US20060115938A1

公开(公告)日：2006-06-01

申请号：US11001514

申请日：2004-11-30

Applicant: Chung-Cheng Wu ,  Wen-Ting Chu

Inventor： Chung-Cheng Wu ,  Wen-Ting Chu

IPC: H01L21/338

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L29/42376 ,  H01L29/66575

Abstract: A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.

Abstract translation: 一种T形栅极结构及其形成方法，包括提供包括至少一个上覆牺牲层的半导体衬底; 光刻地图案化覆盖至少一个牺牲层的抗蚀剂层，以蚀刻开口; 通过所述至少一个牺牲层的厚度形成所述蚀刻开口以暴露所述半导体衬底，所述蚀刻开口包括与底部相比具有较宽上部的锥形横截面; 并且用栅电极材料回填蚀刻的开口以形成栅极结构。

公开(公告)号：US06776177B2

公开(公告)日：2004-08-17

申请号：US10300829

申请日：2002-11-21

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: E04H1528

CPC classification number: E04H15/28 ,  E04H15/40

Abstract: A gardening protective shelter in umbrella shape includes a main rod, a plurality of ribs, a protective cover and a handle. The feature of the present invention is a sliding ring wraps around the main rod and is beneath a runner, a pulling rope each ties to the runner and the sliding ring respectively along the main rod and stretches out from the handle, an open ring and a close ring is at the end of the pulling ropes respectively. Users can pull two control rings to open and close the rib for easier installation and restoration.

Abstract translation: 伞形的园艺防护罩包括主杆，多个肋，保护罩和把手。 本发明的特征是滑环围绕主杆环绕，并且在滑道下方，牵引绳各自分别沿着主杆与滑块和滑环相连，并从手柄伸出，开环和 拉绳的末端分别是闭环。 用户可以拉两个控制环打开和关闭肋条，便于安装和恢复。

公开(公告)号：US06569729B1

公开(公告)日：2003-05-27

申请号：US10199854

申请日：2002-07-19

Applicant: Chung-Cheng Wu ,  Shye-Lin Wu

Inventor： Chung-Cheng Wu ,  Shye-Lin Wu

IPC: H01L21761

CPC classification number: H01L21/84 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823871 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L28/90

Abstract: A method of reducing the aspect ratio for dry etch processes used to form contact hole and storage node openings in composite insulator layers, to expose regions of CMOS devices used for embedded memory cell applications, has been developed. The method features formation of CMOS devices for an embedded memory cell in a recessed region of a semiconductor substrate, while peripheral, higher performing CMOS devices are formed on a non-recessed, SOI layer. Removal of a top portion of a first planarized insulator layer, only in the embedded memory cell region, allows reduction of the aspect ratio of a storage node opening formed in the bottom portion of the first planarized insulator layer. Formation of an overlying, second planarized insulator layer results in a composite insulator layer comprised of a thinned, second planarized insulator layer on the underlying first planarized insulator layer, in the peripheral CMOS device region. The thinned, second planarized insulator component of the composite insulator layer allows reduction of the aspect ratio for formation of a contact hole now defined in the composite insulator layer.

Abstract translation: 已经开发了一种减少用于在复合绝缘体层中形成接触孔和存储节点开口的干式蚀刻工艺的长宽比，以暴露用于嵌入式存储器单元应用的CMOS器件的区域的方法。 该方法的特征在于在半导体衬底的凹陷区域中为嵌入式存储器单元形成CMOS器件，而在非凹入的SOI层上形成外围更高性能的CMOS器件。 仅在嵌入的存储单元区域中去除第一平坦化绝缘体层的顶部，可以减小形成在第一平坦化绝缘体层的底部中的存储节点开口的纵横比。 上覆的第二平坦化绝缘体层的形成导致在外围CMOS器件区域中的下面的第一平坦化绝缘体层上的薄化的第二平坦化绝缘体层的复合绝缘体层。 复合绝缘体层的薄化的第二平坦化绝缘体部件允许减小用于形成现在限定在复合绝缘体层中的接触孔的纵横比。

公开(公告)号：US06548363B1

公开(公告)日：2003-04-15

申请号：US09547237

申请日：2000-04-11

Applicant: Chung-Cheng Wu ,  Bi-Ling Lin ,  Carlos Hernando Diaz

Inventor： Chung-Cheng Wu ,  Bi-Ling Lin ,  Carlos Hernando Diaz

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/7833

Abstract: A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode. There is then formed employing low energy ion implantation shallow junction source-drain extension regions adjacent to the gate electrode. There is then formed source-drain regions to complete the FET device, which exhibits attenuated drain leakage current. The present invention may be employed to fabricate complementary metal-oxide-silicon (CMOS) FET devices of either polarity with attenuated gate induced drain leakage (GIDL) current, short channel effect (SCE) and punch-through leakage current in integrated circuit microelectronics fabrications wherein low power drain is desired.

Abstract translation: 一种用于形成具有衰减栅极感应漏极漏电流的FET器件的方法。 提供了在微电子制造中使用的硅半导体衬底。 形成硅衬底场氧化物（FOX）电介质隔离区域，限定有源硅衬底器件区域。 在衬底上形成采用热氧化的氧化硅栅极氧化物绝缘层。 然后在氧化硅栅极氧化物绝缘层上形成图案化的多晶硅栅极电极层。 然后，将基板和多晶硅栅电极热氧化，以在栅电极的边缘和相邻的硅衬底区域中形成较厚的氧化硅层。 然后从与栅电极相邻的硅衬底区域中回蚀更厚的氧化硅层。 然后形成采用与栅电极相邻的低能离子注入浅结源极 - 漏极扩展区。 然后形成源极 - 漏极区以完成FET器件，其表现出衰减的漏极漏电流。 本发明可用于在集成电路微电子器件制造中制造具有衰减栅极感应漏极泄漏（GIDL）电流，短沟道效应（SCE）和穿通漏电流两种极性的互补金属氧化物 - 硅（CMOS）FET器件 其中期望低功率消耗。

公开(公告)号：US6069052A

公开(公告)日：2000-05-30

申请号：US706652

申请日：1996-10-07

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L28/84

Abstract: The present invention provides a process and a structure for increasing a capacitance of a stack capacitor. The process includes steps of: a) forming a contact hole on a silicon substrate having an oxide layer, b) forming a polysilicon contact plug of a first polysilicon layer in the contact hole; c) forming a second gibbous polysilicon layer on a surface of the contact plug, and d) forming a third polysilicon layer above the gibbous polysilicon layer and a portion of the oxide layer to form the stack capacitor, wherein the gibbous polysilicon layer increases the capacitance of the stack capacitor.

Abstract translation: 本发明提供一种用于增加堆叠电容器的电容的工艺和结构。 该方法包括以下步骤：a）在具有氧化物层的硅衬底上形成接触孔，b）在接触孔中形成第一多晶硅层的多晶硅接触插塞; c）在所述接触插塞的表面上形成第二起绒多晶硅层，以及d）在所述起伏多晶硅层上方形成第三多晶硅层和所述氧化物层的一部分以形成所述堆叠电容器，其中所述起伏多晶硅层增加所述电容 的堆叠电容器。

公开(公告)号：US6033963A

公开(公告)日：2000-03-07

申请号：US385523

申请日：1999-08-30

Applicant: Jenn Ming Huang ,  Chi-Wen Su ,  Chung-Cheng Wu ,  Shui-Hung Chen

Inventor： Jenn Ming Huang ,  Chi-Wen Su ,  Chung-Cheng Wu ,  Shui-Hung Chen

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/49

CPC classification number: H01L29/6659 ,  H01L21/76838 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming a metal gate for a CMOS device using a replacement gate process wherein sidewall spacers are formed on a dummy electrode prior to forming the metal gate allowing source and drain formation prior to metal gate formation and a tungsten layer is selectively deposited to act as an each or CMP stop and to reduce source and drain resistance. The process begins by forming a dummy gate oxide layer and a polysilicon dummy gate electrode layer on a substrate structure and patterning them to form a dummy gate. Lightly doped source and drain regions are formed by ion implantation using the dummy gate as an implant mask. Spacers are formed on the sidewalls of the dummy gate. Source and drain regions are formed by implanting ions using,the dummy gate and spacers as an implant mask and performing a rapid thermal anneal. A tungsten layer is selectively deposited on the dummy gate electrode and the source and drain regions. A blanket dielectric layer is formed over the dummy gate and the substrate structure. The blanket dielectric layer is planarized using a chemical mechanical polishing process stopping on the tungsten layer. The tungsten layer overlying the dummy gate and the dummy gate are removed, thereby forming a gate opening. A gate oxide layer and a metal gate electrode layer are formed in the gate opening. The gate electrode layer is planarized to form a metal gate, stopping on the blanket dielectric layer. Alternatively, the dummy gate electrode can be composed of silicon nitride and the selectively deposited tungsten layer can be omitted.

Abstract translation: 使用替代栅极工艺形成用于CMOS器件的金属栅极的方法，其中在形成金属栅极之前在虚设电极上形成侧壁间隔物，其允许在金属栅极形成之前的源极和漏极形成以及选择性地沉积钨层以起作用 作为每个或CMP停止并减少源极和漏极电阻。 该过程开始于在衬底结构上形成虚拟栅极氧化物层和多晶硅虚拟栅极电极层并将其图案化以形成虚拟栅极。 通过使用伪栅极作为注入掩模的离子注入形成轻掺杂源极和漏极区域。 隔板形成在虚拟门的侧壁上。 通过使用伪栅极和间隔物作为注入掩模注入离子并执行快速热退火来形成源区和漏区。 钨层被选择性地沉积在虚拟栅极电极和源极和漏极区域上。 在伪栅极和衬底结构之上形成覆盖层的介电层。 使用在钨层上停止的化学机械抛光工艺来平坦化覆盖绝缘层。 覆盖虚拟栅极和虚拟栅极的钨层被去除，从而形成栅极开口。 栅极氧化层和金属栅极电极层形成在栅极开口中。 栅极电极层被平坦化以形成金属栅极，停止在覆盖电介质层上。 或者，伪栅电极可以由氮化硅构成，并且可以省略选择性沉积的钨层。

公开(公告)号：US5726086A

公开(公告)日：1998-03-10

申请号：US746842

申请日：1996-11-18

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: The present invention discloses a method of fabricating self-aligned cylindrical capacitor in stack Dynamic Random Access Memory (Stack DRAM) cells. The polysilicon stud is filled in the contact window of the source region of a metal-oxide-semiconductor field effect transistor (MOSFET). Then the polysilicon spacers are formed on the sidewalls of the first polysilicon stud. The cylindrical capacitor storage node of the DRAM capacitor of the present invention has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices. Furthermore, this new process only needs one lithography photomask to open contact window compared with the conventional process which needs two lithography photomasks, that further reduces the production cost.

Abstract translation: 本发明公开了一种在堆叠动态随机存取存储器（Stack DRAM）单元中制造自对准圆柱形电容器的方法。 多晶硅螺柱填充在金属氧化物半导体场效应晶体管（MOSFET）的源极区域的接触窗口中。 然后，多晶硅间隔物形成在第一多晶硅柱的侧壁上。 本发明的DRAM电容器的圆柱形电容器存储节点具有大得多的表面积，以便增加DRAM电容器的电容值，这可以实现集成电路器件的高封装密度。 此外，与需要两个光刻光掩模的常规工艺相比，该新工艺仅需要一个光刻光掩模来打开接触窗口，这进一步降低了生产成本。

公开(公告)号：US5650346A

公开(公告)日：1997-07-22

申请号：US557546

申请日：1995-11-14

Applicant: Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

Inventor： Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/11558

Abstract: A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by:forming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.

Abstract translation: 一种MOSFET器件，其具有覆盖有介电材料的衬底，该器件包括电容耦合到多晶硅电极的多个掩埋导体，其通过以下方式制成：在包含MOSFET器件的区域之间形成通过离子注入穿过衬底中的多个位线的区域 栅极氧化物以预定图案进入衬底，并且在电介质材料上形成跨越位线的多晶硅电极。