公开(公告)号：US07187046B2

公开(公告)日：2007-03-06

申请号：US10831868

申请日：2004-04-26

Applicant: Chung-Cheng Wu ,  Shye-Lin Wu

Inventor： Chung-Cheng Wu ,  Shye-Lin Wu

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/962

Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape. An anneal procedure results creation of a source/drain region of a first conductivity type in portions of the first SOI fin type shape underlying the first doped insulator layer, and creation of a source/drain region of a second conductivity type in portions of the second SOI fin type shape underlying the second doped insulator layer. Selective deposition of tungsten on exposed top surface of the source/drain regions is then employed to decrease source/drain resistance.

Abstract translation: 已经开发了形成具有N沟道器件和形成在同一SOI层中的P沟道器件的FINFET CMOS器件结构的方法。 该方法特征是形成两个平行的SOI鳍式结构，随后在SOI鳍型结构的侧面上形成栅极绝缘体，并且界定在栅极绝缘体层之间穿过SOI鳍型结构的导电栅极结构。 在第一SOI鳍型形状的暴露的顶表面上形成第一导电类型的掺杂绝缘体层，而在第二SOI鳍型形状的暴露的顶表面上形成第二导电类型的第二掺杂绝缘体层。 退火程序导致在第一掺杂绝缘体层下面的第一SOI鳍型形状的部分中产生第一导电类型的源极/漏极区域，并且在第二导电类型的部分中产生第二导电类型的源极/漏极区域 第二掺杂绝缘体层下方的SOI鳍型。 然后选择性沉积钨在源极/漏极区域的暴露的顶表面上，以降低源极/漏极电阻。

公开(公告)号：US06770516B2

公开(公告)日：2004-08-03

申请号：US10235253

申请日：2002-09-05

Applicant: Chung Cheng Wu ,  Shye-Lin Wu

Inventor： Chung Cheng Wu ,  Shye-Lin Wu

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/962

Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape. An anneal procedure results creation of a source/drain region of a first conductivity type in portions of the first SOI fin type shape underlying the first doped insulator layer, and creation of a source/drain region of a second conductivity type in portions of the second SOI fin type shape underlying the second doped insulator layer. Selective deposition of tungsten on exposed top surface of the source/drain regions is then employed to decrease source/drain resistance.

Abstract translation: 已经开发了形成具有N沟道器件和形成在同一SOI层中的P沟道器件的FINFET CMOS器件结构的方法。 该方法特征是形成两个平行的SOI鳍式结构，随后在SOI鳍型结构的侧面上形成栅极绝缘体，并且界定在栅极绝缘体层之间穿过SOI鳍型结构的导电栅极结构。 在第一SOI鳍型形状的暴露的顶表面上形成第一导电类型的掺杂绝缘体层，而在第二SOI鳍型形状的暴露的顶表面上形成第二导电类型的第二掺杂绝缘体层。 退火程序导致在第一掺杂绝缘体层下面的第一SOI鳍型形状的部分中产生第一导电类型的源极/漏极区域，并且在第二导电类型的部分中产生第二导电类型的源极/漏极区域 第二掺杂绝缘体层下方的SOI鳍型。 然后选择性沉积钨在源极/漏极区域的暴露的顶表面上，以降低源极/漏极电阻。

公开(公告)号：US06569729B1

公开(公告)日：2003-05-27

申请号：US10199854

申请日：2002-07-19

Applicant: Chung-Cheng Wu ,  Shye-Lin Wu

Inventor： Chung-Cheng Wu ,  Shye-Lin Wu

IPC: H01L21761

CPC classification number: H01L21/84 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823871 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L28/90

Abstract: A method of reducing the aspect ratio for dry etch processes used to form contact hole and storage node openings in composite insulator layers, to expose regions of CMOS devices used for embedded memory cell applications, has been developed. The method features formation of CMOS devices for an embedded memory cell in a recessed region of a semiconductor substrate, while peripheral, higher performing CMOS devices are formed on a non-recessed, SOI layer. Removal of a top portion of a first planarized insulator layer, only in the embedded memory cell region, allows reduction of the aspect ratio of a storage node opening formed in the bottom portion of the first planarized insulator layer. Formation of an overlying, second planarized insulator layer results in a composite insulator layer comprised of a thinned, second planarized insulator layer on the underlying first planarized insulator layer, in the peripheral CMOS device region. The thinned, second planarized insulator component of the composite insulator layer allows reduction of the aspect ratio for formation of a contact hole now defined in the composite insulator layer.

Abstract translation: 已经开发了一种减少用于在复合绝缘体层中形成接触孔和存储节点开口的干式蚀刻工艺的长宽比，以暴露用于嵌入式存储器单元应用的CMOS器件的区域的方法。 该方法的特征在于在半导体衬底的凹陷区域中为嵌入式存储器单元形成CMOS器件，而在非凹入的SOI层上形成外围更高性能的CMOS器件。 仅在嵌入的存储单元区域中去除第一平坦化绝缘体层的顶部，可以减小形成在第一平坦化绝缘体层的底部中的存储节点开口的纵横比。 上覆的第二平坦化绝缘体层的形成导致在外围CMOS器件区域中的下面的第一平坦化绝缘体层上的薄化的第二平坦化绝缘体层的复合绝缘体层。 复合绝缘体层的薄化的第二平坦化绝缘体部件允许减小用于形成现在限定在复合绝缘体层中的接触孔的纵横比。

公开(公告)号：US07368371B2

公开(公告)日：2008-05-06

申请号：US11453801

申请日：2006-06-16

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01L21/8213 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

Abstract: A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n− silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.

Abstract translation: 公开了一种形成碳化硅肖特基二极管的方法。 这些过程只需要两个照相掩模。 工艺如下：首先，提供具有碳化硅漂移层的n + - 碳化硅衬底。 然后在漂移层上形成硅层。 进行离子注入以掺杂硅层。 之后，将掺杂硅层图案化以限定有源区。 然后通过氧化硅层并通过使用掺杂硅层作为扩散源形成保护环，随后进行热氧化以形成厚氧化物层。 然后通过稀释HF浸渍或通过BOE（缓冲氧化物蚀刻）溶液浸渍除去漂移层上的薄氧化物层。 此后，沉积顶层金属层并图案化以将其定义为阳极。 在去除背面层之后，形成用作阴极的金属层。

公开(公告)号：US20070293028A1

公开(公告)日：2007-12-20

申请号：US11453799

申请日：2006-06-16

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01L21/26513 ,  H01L21/2658 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/872

Abstract: A method of forming a power Schottky rectifier device is disclosed. The Schottky rectifier device including LOCOS structure and two p doped layers formed thereunder to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n− drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n− drift layer; a pair of field oxide regions and termination field oxide region formed into the n− drift layer and each spaced from each other by the mesas. A stack of metal layers formed of Ti/Ni/Ag are formed atop the front surface. A RTP (rapid thermal process) is then followed to form a Schottky barrier diode. Alternatively, the stack metal layers are formed of Ti/TiN/Al. Yet, the Al is formed after RTP. Subsequently, the top metal layer is patterned to form an anode electrode.

Abstract translation: 公开了一种形成功率肖特基整流器件的方法。 肖特基整流器包括LOCOS结构和两个p掺杂层形成在其下面，以避免击穿电压过早。 肖特基整流器件包括：形成在n +衬底上的n-漂移层; 形成在与n漂移层相对的n +衬底的表面上的阴极金属层; 一对场氧化物区域和终止场氧化物区域，形成在n漂移层中，并且每个通过台面彼此间隔开。 由Ti / Ni / Ag形成的一叠金属层形成在前表面的顶部。 然后按照RTP（快速热处理）形成肖特基势垒二极管。 或者，堆叠金属层由Ti / TiN / Al形成。 然而，Al是在RTP之后形成的。 随后，对顶部金属层进行图案化以形成阳极电极。

公开(公告)号：US20070293001A1

公开(公告)日：2007-12-20

申请号：US11453801

申请日：2006-06-16

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8234

CPC classification number: H01L21/8213 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

Abstract: A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n− silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.

Abstract translation: 公开了一种形成碳化硅肖特基二极管的方法。 这些过程只需要两个照相掩模。 工艺如下：首先，提供具有碳化硅漂移层的n + - 碳化硅衬底。 然后在漂移层上形成硅层。 进行离子注入以掺杂硅层。 之后，将掺杂硅层图案化以限定有源区。 然后通过氧化硅层并通过使用掺杂硅层作为扩散源形成保护环，随后进行热氧化以形成厚氧化物层。 然后通过稀释HF浸渍或通过BOE（缓冲氧化物蚀刻）溶液浸渍除去漂移层上的薄氧化物层。 此后，沉积顶层金属层并图案化以将其定义为阳极。 在去除背面层之后，形成用作阴极的金属层。

公开(公告)号：US06342422B1

公开(公告)日：2002-01-29

申请号：US09439433

申请日：1999-11-15

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/28035 ,  H01L21/28247 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. A first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, the first silicon layer, and the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and the first dielectric layer is removed. A second silicon layer is formed on the semiconductor substrate and on the first silicon layer. Another doping step is performed to dope the second silicon layer. A series of process is then performed to form a metal silicide layer on the second silicon layer and also to diffuse and activate the doped dopants.

Abstract translation: 在半导体衬底上形成栅极绝缘体层，然后在栅极绝缘体层上形成第一硅层。 第一介电层形成在第一硅层之上。 通过去除栅极绝缘体层，第一硅层和第一介电层的一部分来限定栅极区域。 执行使用低能量注入或等离子体浸没的掺杂步骤以掺杂衬底，以在由栅极区域未覆盖的区域下在衬底中形成扩展的源极/漏极结。 在栅极区域的侧壁上形成未掺杂的间隔结构，并且去除第一介电层。 在半导体衬底上和第一硅层上形成第二硅层。 执行另一掺杂步骤以掺杂第二硅层。 然后执行一系列处理以在第二硅层上形成金属硅化物层，并且还扩散和激活掺杂的掺杂剂。

公开(公告)号：US06255167B1

公开(公告)日：2001-07-03

申请号：US09325810

申请日：1999-06-04

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of fabricating buried bit line flash EEROM cells with shallow trench floating gates for suppressing the short channel effect is disclosed. The method includes the following steps. First, a first polysilicon layer with conductive impurities and a nitride capping layer are sequentially formed on a silicon substrate. The nitride cap layer serves as an anti-reflection coating (ARC) layer for improving the resolution of lithography. Then a photo-mask pattern on the ARC layer is formed to define trench regions, an anisotropic etching is performed to etch away unmasked portions of the nitride cap layer through the first polysilicon layer and slightly recess the silicon substrate using the patterned mask as a mask. After removing the patterned mask, a thermal annealed process is performed to grow a polyoxide layer on the sidewall of the first polysilicon layer and an thin oxynitride layer on the surface of the recessed silicon substrate. In the meantime, the buried bit lines are formed where each bit line is a layer beneath the first polysilicon layer. The trenches are then refilled with a silicon layer. A planarization process then follows. Subsequently, an interpoly dielectric layer is formed. Finally, a second polysilicon layer is formed and pattered to define word lines.

Abstract translation: 公开了一种用浅沟槽浮动栅极制造掩埋位线闪光EEROM单元以抑制短沟道效应的方法。 该方法包括以下步骤。 首先，在硅衬底上依次形成具有导电杂质的第一多晶硅层和氮化物覆盖层。 氮化物覆盖层用作抗反射涂层（ARC）层，用于提高光刻的分辨率。 然后形成ARC层上的光掩模图案以限定沟槽区域，执行各向异性蚀刻以蚀刻通过第一多晶硅层去除氮化物覆盖层的未屏蔽部分，并使用图案化掩模作为掩模稍微凹入硅衬底 。 在去除图案化掩模之后，进行热退火工艺以在第一多晶硅层的侧壁和凹入的硅衬底的表面上形成薄氧氮化物层上生长多氧化物层。 同时，形成掩埋位线，其中每个位线是第一多晶硅层下面的层。 然后用硅层重新填充沟槽。 然后，进行平面化处理。 接着，形成间隔电介质层。 最后，形成第二多晶硅层并图案化以限定字线。

公开(公告)号：US06207505B1

公开(公告)日：2001-03-27

申请号：US09326857

申请日：1999-06-07

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21336

CPC classification number: H01L21/28273 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825

Abstract: A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is then removed. A polysilicon film is deposited over the substrate 2 and then oxidized into sacrificial oxide layer. After stripping the sacrificial oxide layer, a rugged topography is then formed on the doped substrate regions. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

Abstract translation: 公开了一种用于制造高速和高密度非易失性存储单元的方法。 首先，制备具有限定的场氧化物和有源区的半导体衬底。 沉积堆叠的氧化硅/氮化硅层，然后定义隧道氧化物区域。 在非隧道区域上生长厚的氧化物。 在去除掩模氮化硅层之后，通过离子注入和热退火形成源极和漏极。 然后去除垫氧化膜。 多晶硅膜沉积在衬底2上，然后氧化成牺牲氧化物层。 在剥离牺牲氧化物层之后，在掺杂的衬底区域上形成粗糙的形貌。 此后，在粗糙的掺杂衬底区域上生长薄氧化物以形成坚固的隧道氧化物。 最后，依次形成浮栅，互补电介质和控制栅，并结束存储单元。

公开(公告)号：US06171893B2

公开(公告)日：2001-01-09

申请号：US09366606

申请日：1999-08-03

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L218238

CPC classification number: H01L21/823418 ,  H01L21/823443 ,  H01L21/823456 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0266

Abstract: The method of forming MOS transistors includes the following steps. First, isolation regions are formed in the semiconductor substrate to separate the semiconductor substrate into an ESD protective region and a functional region. A gate insulator layer is formed on the substrate and a polysilicon layer is formed on the gate insulator layer. The polysilicon layer is then patterned to form gate structures on the ESD protective region and the functional region. The semiconductor substrate is doped for forming a first doped region and an insulator layer is formed over the semiconductor substrate. A portion of the insulator layer and a portion of the gate insulator layer are removed to form spacer structures and an insulator block. The semiconductor substrate is doped for forming a second doped region. An insulator opening is defined within the insulator block. The semiconductor substrate is then doped for forming a third doped region. In the preferred embodiments, the third doped region has opposite type dopants with the second doped region and the first doped region. A first thermal annealing is then performed to the semiconductor substrate to drive in dopants. A metal layer is then formed on the semiconductor substrate and a second thermal annealing is performed to the semiconductor substrate to form a metal silicide layer on the gate structures, and on the substrate over the second doped region and the third doped region. Finally, unreacted portions of the metal layer are removed.

Abstract translation: 形成MOS晶体管的方法包括以下步骤。 首先，在半导体衬底中形成隔离区以将半导体衬底分离成ESD保护区和功能区。 在衬底上形成栅极绝缘体层，并且在栅极绝缘体层上形成多晶硅层。 然后将多晶硅层图案化以在ESD保护区域和功能区域上形成栅极结构。 掺杂半导体衬底以形成第一掺杂区域，并且在半导体衬底上形成绝缘体层。 去除绝缘体层的一部分和栅极绝缘体层的一部分以形成间隔物结构和绝缘体块。 掺杂半导体衬底以形成第二掺杂区域。 绝缘体开口限定在绝缘体块内。 然后掺杂半导体衬底以形成第三掺杂区域。 在优选实施例中，第三掺杂区域具有与第二掺杂区域和第一掺杂区域相反的掺杂剂。 然后对半导体衬底进行第一热退火以在掺杂剂中驱动。 然后在半导体衬底上形成金属层，并对半导体衬底进行第二热退火，以在栅极结构上形成金属硅化物层，并在第二掺杂区域和第三掺杂区域上形成衬底。 最后，除去金属层的未反应部分。