公开(公告)号：USRE34241E

公开(公告)日：1993-05-04

申请号：US490801

申请日：1990-03-08

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: H04J3/06

CPC classification number: H04J3/0605

Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of the bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.

公开(公告)号：US4843265A

公开(公告)日：1989-06-27

申请号：US217142

申请日：1988-06-30

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G05F1/46

CPC classification number: G05F1/466 ,  Y10S323/907

Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

Abstract translation: 可以在单片集成电路中制造的类型的温度和处理补偿时间延迟电路利用连接到充电电容器（14）的端子的场效应晶体管（FET）（12）。 连接到FET（12）的栅极的偏置电压随着温度而变化，以补偿由于温度变化而从电容器（14）流过FET（12）的电流的变化。 偏置电压也可以从一个集成电路到另一个集成电路的变化，以补偿由集成电路的处理变化引起的FET阈值电压的变化。

公开(公告)号：US4730346A

公开(公告)日：1988-03-08

申请号：US13911

申请日：1987-02-12

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: H04J3/06 ,  H04L7/08

CPC classification number: H04J3/0605

Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.

Abstract translation: 通过将串行比特流的最后一位与串行比特流的预定数量的先前比特相组合来定位串行比特流中的嵌入的成帧位模式，该预定数量的串行比特流的先前比特间隔开成帧位的比特的间距 模式，并且测试这些位的组合以确定组合是否匹配成帧位模式的一部分。 如果没有发生匹配，则组合在一起的位被改变成不会导致匹配的位模式，当这些位（除了被忽略的最老位除外）被再次与串行的新位组合时 位流，无论新位的逻辑状态如何。 以这种方式，当它们到达并被组合和测试时，所有位将最终被改变，除了作为帧位模式的一部分的位之外。

公开(公告)号：US5339076A

公开(公告)日：1994-08-16

申请号：US876771

申请日：1992-04-27

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G06F5/00 ,  G06F17/21 ,  G06T9/00 ,  H03M7/30 ,  H03M7/46

CPC classification number: H03M7/3086 ,  G06T9/005

Abstract: A data compression/decompression processor implements a modified Ziv-Lempel ("LZ") coding technique. The processor includes three modules, an interface, a coder-decoder ("CODEC"), and a MODEL. The CODEC and the MODEL modules together form compression engine, in which the CODEC provides variable length coding and data packing, and the MODEL implements the LZ processing. The MODEL uses content addressable memory ("CAM") in encoding mode for text storage and character matching, and uses CAM in decoding mode as an on-chip RAM to obtain high speed access.

Abstract translation: 数据压缩/解压缩处理器实现修改的Ziv-Lempel（“LZ”）编码技术。 处理器包括三个模块，一个接口，一个编码器解码器（“CODEC”）和一个MODEL。 CODEC和MODEL模块一起形成压缩引擎，其中CODEC提供可变长度编码和数据打包，MODEL实现LZ处理。 MODEL在编码模式下使用内容可寻址存储器（“CAM”）进行文本存储和字符匹配，并将解码模式下的CAM用作片上RAM以获得高速访问。

公开(公告)号：US4894791A

公开(公告)日：1990-01-16

申请号：US828230

申请日：1986-02-10

Applicant: Ching-Lin Jiang ,  William J. Podkowa

Inventor： Ching-Lin Jiang ,  William J. Podkowa

IPC: H03K5/04 ,  H03K19/003

CPC classification number: H03K5/04 ,  H03K19/00323

Abstract: A delay circuit that can be implemented in a monolithic integrated circuit includes a plurality of capacitor/laser-fusible link series pairs. Delay of a binary output signal of the circuit with respect to an input transition is directly proportional to the amount of capacitance connected into the circuit. Because the laser-fusible links can selectively be opened with a laser, the amount of capacitance connected into the circuit can incrementally be reduced; thus, the delay of the circuit is reducibly adjustable to a desired value. By including a plurality of conductive element/laser-fusible link series pairs in the delay circuit, the delay of the circuit is also increasingly adjustable. A method for economically adjusting the delay of each of many like delay circuits embodied in a semiconductor wafer includes measuring a sample of the delays of the delay circuits, calculating an average delay, determining the difference between a desired delay and the average delay to determine an incremental amount of delay to eliminate or to add, determining from predetermined data which fusible links should be opened, and using a laser beam to open the appropriate links.

Abstract translation: 可以在单片集成电路中实现的延迟电路包括多个电容器/激光可熔链节串联对。 相对于输入跃迁的电路的二进制输出信号的延迟与连接到电路中的电容量成正比。 因为激光熔丝可以选择性地用激光打开，连接到电路中的电容量可以逐渐减小; 因此，电路的延迟可以可调节到期望的值。 通过在延迟电路中包括多个导电元件/激光可熔链节串联对，电路的延迟也越来越可调。 用于经济地调节在半导体晶片中实现的许多类似延迟电路中的每一个的延迟的方法包括测量延迟电路的延迟的样本，计算平均延迟，确定期望延迟和平均延迟之间的差以确定 消除或添加的增量的延迟量，从预定数据确定哪个可熔断链接应该被打开，以及使用激光束打开适当的链接。

公开(公告)号：US4545035A

公开(公告)日：1985-10-01

申请号：US400171

申请日：1982-07-20

Applicant: Daniel C. Guterman ,  Ching-Lin Jiang

Inventor： Daniel C. Guterman ,  Ching-Lin Jiang

IPC: G11C14/00 ,  H01L27/108 ,  G11C11/40

CPC classification number: H01L27/108 ,  G11C14/00

Abstract: A compact memory cell combines a volatile dynamic storage section with a shadow nonvolatile section in two vertically stacked element arrays.

Abstract translation: 紧凑型存储单元将易失性动态存储部分与两个垂直堆叠的元件阵列中的阴影非易失部分组合。

公开(公告)号：US4360903A

公开(公告)日：1982-11-23

申请号：US265994

申请日：1980-09-10

Applicant: Robert S. Plachno ,  Ching-Lin Jiang

Inventor： Robert S. Plachno ,  Ching-Lin Jiang

IPC: G11C11/406 ,  G11C11/4063 ,  G11C7/00

CPC classification number: G11C11/406 ,  G11C11/4063

Abstract: A clocking system for a self-refreshed dynamic memory (10) for reading data stored in a memory cell (30) and including clocking circuitry (68) includes detecting changes in an address signal (60). The method further includes generating a memory refresh signal (64, 66) in response to detecting changes in the address signal (60). The memory refresh signal (66) is applied to the semiconductor memory circuit (30) for refreshing data stored in the memory cells of the semiconductor memory circuit (30). After the application of the memory refresh signal (66) to the semiconductor memory circuit (30) the address signal (16) is applied to the semiconductor memory circuit (30) for accessing the addressed memory cell to thereby read the data stored therein. The clocking circuitry (68) is reset and precharged during the application of the refresh signal (66) to the semiconductor memory circuit (30).

Abstract translation: PCT No.PCT / US80 / 01162 Sec。 371日期1980年9月10日 102（e）1980年9月10日PCT PCT日期为1980年9月10日PCT公布。 第WO82 / 00915号公报 日期：1982年3月18日。一种用于读取存储在存储单元（30）中并包括时钟电路（68）的数据的自动刷新动态存储器（10）的计时系统，包括检测地址信号（60）中的变化。 该方法还包括响应于检测到地址信号（60）中的变化而产生存储器刷新信号（64,66）。 存储器刷新信号（66）被施加到半导体存储器电路（30），用于刷新存储在半导体存储器电路（30）的存储单元中的数据。 在向半导体存储器电路（30）施加存储器刷新信号（66）之后，将地址信号（16）施加到半导体存储器电路（30），以访问所寻址的存储器单元，从而读取存储在其中的数据。 在刷新信号（66）施加到半导体存储器电路（30）期间，时钟电路（68）被复位并被预充电。

公开(公告)号：US4306221A

公开(公告)日：1981-12-15

申请号：US25138

申请日：1979-03-29

Applicant: Ching-Lin Jiang ,  Chi-Shin Wang

Inventor： Ching-Lin Jiang ,  Chi-Shin Wang

IPC: H03M1/00 ,  H03K13/03

CPC classification number: H03M1/14

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract translation: 通过逐次逼近的模数转换通过电荷耦合器件实现。 在转换过程中，比较两个电荷，每个比较产生一个多位数的一位。 通过在每次比较之后增加较小的比较电荷，消除了作为逐次逼近处理的一部分的电荷减去的需要。

公开(公告)号：US4171521A

公开(公告)日：1979-10-16

申请号：US802835

申请日：1977-06-02

Applicant: Chi-Shin Wang ,  Ching-Lin Jiang

Inventor： Chi-Shin Wang ,  Ching-Lin Jiang

IPC: H03M1/00 ,  H03K13/03

CPC classification number: H03M1/442

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract translation: 通过逐次逼近的模数转换通过电荷耦合器件实现。 在转换过程中，比较两个电荷，每个比较产生一个多位数的一位。 通过在每次比较之后增加较小的比较电荷，消除了作为逐次逼近处理的一部分的电荷减去的需要。

公开(公告)号：US5351208A

公开(公告)日：1994-09-27

申请号：US874489

申请日：1992-04-27

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory is provided that includes a memory cell and a first plurality of lines connected directly to the gates of access transistors to this memory cell. These access transistors are further connected to a second plurality of lines. The first and second plurality of lines each perform different functions during read, write, and comparison modes. In another embodiment of the present invention, p-channel transistors are used for a match transistor and its associated pass transistors.

Abstract translation: 提供了一种内容可寻址存储器，其包括存储单元和直接连接到存储单元的存取晶体管的栅极的第一多条线。 这些存取晶体管进一步连接到第二组线。 第一和第二组线在读，写和比较模式下都执行不同的功能。 在本发明的另一个实施例中，p沟道晶体管用于匹配晶体管及其相关联的传输晶体管。