公开(公告)号：US4306221A

公开(公告)日：1981-12-15

申请号：US25138

申请日：1979-03-29

Applicant: Ching-Lin Jiang ,  Chi-Shin Wang

Inventor： Ching-Lin Jiang ,  Chi-Shin Wang

IPC: H03M1/00 ,  H03K13/03

CPC classification number: H03M1/14

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract translation: 通过逐次逼近的模数转换通过电荷耦合器件实现。 在转换过程中，比较两个电荷，每个比较产生一个多位数的一位。 通过在每次比较之后增加较小的比较电荷，消除了作为逐次逼近处理的一部分的电荷减去的需要。

公开(公告)号：US4171521A

公开(公告)日：1979-10-16

申请号：US802835

申请日：1977-06-02

Applicant: Chi-Shin Wang ,  Ching-Lin Jiang

Inventor： Chi-Shin Wang ,  Ching-Lin Jiang

IPC: H03M1/00 ,  H03K13/03

CPC classification number: H03M1/442

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract translation: 通过逐次逼近的模数转换通过电荷耦合器件实现。 在转换过程中，比较两个电荷，每个比较产生一个多位数的一位。 通过在每次比较之后增加较小的比较电荷，消除了作为逐次逼近处理的一部分的电荷减去的需要。

公开(公告)号：US4645943A

公开(公告)日：1987-02-24

申请号：US660937

申请日：1984-10-15

Applicant: John W. Smith, Jr. ,  Francis A. Scherpenberg ,  Ching-Lin Jiang ,  Michael L. Bolan

Inventor： John W. Smith, Jr. ,  Francis A. Scherpenberg ,  Ching-Lin Jiang ,  Michael L. Bolan

IPC: G06F1/30 ,  H02J9/06 ,  H02J9/02

CPC classification number: G06F1/30 ,  H02J9/061 ,  Y10T307/615 ,  Y10T307/625

Abstract: A space-saving back-up power supply apparatus has length and width dimensions substantially the same as those of a conventional integrated circuit connector. The apparatus includes sockets arranged on its top for making connection to a socket-pluggable integrated circuit such as a standard CMOS RAM, and the apparatus has pins extending from its bottom for making connection to a printed circuit board or connector of a host electronic system. Control circuitry and one or more batteries are located within the apparatus. The back-up power supply is operative to provide power to the socket-pluggable integrated circuit even if the normal power supply of the host electronic system is short-circuited. The control circuitry of the back-up power supply controls the chip enable signal and performs a battery test upon power-up.

Abstract translation: 节省空间的备用电源设备的长度和宽度尺寸基本上与传统的集成电路连接器相同。 该设备包括设置在其顶部的插座，用于连接到诸如标准CMOS RAM的插座可插拔集成电路，并且该设备具有从其底部延伸的引脚，用于连接到主机电子系统的印刷电路板或连接器。 控制电路和一个或多个电池位于设备内。 即使主机电子系统的正常电源短路，备用电源也可以为插座可插拔集成电路供电。 备用电源的控制电路控制芯片使能信号，并在上电时执行电池测试。

公开(公告)号：US4613959A

公开(公告)日：1986-09-23

申请号：US568960

申请日：1984-01-06

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G06F11/16 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003 ,  H03K19/173 ,  G11C7/00 ,  G06F11/00 ,  H01J19/82 ,  H03K17/82

CPC classification number: G11C29/83 ,  G06F11/16 ,  G11C17/16 ,  H03K19/00392

Abstract: A redundancy circuit that consumes no power before or after activation switches a pair of output nodes from a first set of complementary logic levels to an inverted set when it is activated by blowing a pair of fuses.

Abstract translation: 在激活之前或之后消耗功率的冗余电路在通过吹一对保险丝而被激活时将一对输出节点从第一组互补逻辑电平切换到反相集合。

公开(公告)号：US5532958A

公开(公告)日：1996-07-02

申请号：US135722

申请日：1993-11-24

Applicant: Ching-Lin Jiang ,  Clark R. Williams

Inventor： Ching-Lin Jiang ,  Clark R. Williams

IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28 ,  G11C11/40

CPC classification number: G06F5/065 ,  G11C11/41 ,  G11C11/412 ,  G11C19/287 ,  G11C8/16

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

公开(公告)号：USRE34241E

公开(公告)日：1993-05-04

申请号：US490801

申请日：1990-03-08

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: H04J3/06

CPC classification number: H04J3/0605

Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of the bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.

公开(公告)号：US5162757A

公开(公告)日：1992-11-10

申请号：US499853

申请日：1990-03-27

Applicant: Clark R. Williams ,  Ching-Lin Jiang

Inventor： Clark R. Williams ,  Ching-Lin Jiang

IPC: H03B5/36 ,  H03K3/014 ,  H03K3/354 ,  H03L3/00

CPC classification number: H03B5/06 ,  H03B5/364 ,  H03K3/014 ,  H03K3/3545 ,  H03L3/00 ,  H03B2200/0012

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during startup.

Abstract translation: 一种低功率晶体控制CMOS振荡器，其中在输出放大器的第一级提供长而宽的附加晶体管。 这可以防止输出放大器在启动期间从初级放大器级转移太多的电流。

公开(公告)号：US4843265A

公开(公告)日：1989-06-27

申请号：US217142

申请日：1988-06-30

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G05F1/46

CPC classification number: G05F1/466 ,  Y10S323/907

Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

Abstract translation: 可以在单片集成电路中制造的类型的温度和处理补偿时间延迟电路利用连接到充电电容器（14）的端子的场效应晶体管（FET）（12）。 连接到FET（12）的栅极的偏置电压随着温度而变化，以补偿由于温度变化而从电容器（14）流过FET（12）的电流的变化。 偏置电压也可以从一个集成电路到另一个集成电路的变化，以补偿由集成电路的处理变化引起的FET阈值电压的变化。

公开(公告)号：US4730346A

公开(公告)日：1988-03-08

申请号：US13911

申请日：1987-02-12

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: H04J3/06 ,  H04L7/08

CPC classification number: H04J3/0605

Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.

Abstract translation: 通过将串行比特流的最后一位与串行比特流的预定数量的先前比特相组合来定位串行比特流中的嵌入的成帧位模式，该预定数量的串行比特流的先前比特间隔开成帧位的比特的间距 模式，并且测试这些位的组合以确定组合是否匹配成帧位模式的一部分。 如果没有发生匹配，则组合在一起的位被改变成不会导致匹配的位模式，当这些位（除了被忽略的最老位除外）被再次与串行的新位组合时 位流，无论新位的逻辑状态如何。 以这种方式，当它们到达并被组合和测试时，所有位将最终被改变，除了作为帧位模式的一部分的位之外。

公开(公告)号：US5339076A

公开(公告)日：1994-08-16

申请号：US876771

申请日：1992-04-27

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G06F5/00 ,  G06F17/21 ,  G06T9/00 ,  H03M7/30 ,  H03M7/46

CPC classification number: H03M7/3086 ,  G06T9/005

Abstract: A data compression/decompression processor implements a modified Ziv-Lempel ("LZ") coding technique. The processor includes three modules, an interface, a coder-decoder ("CODEC"), and a MODEL. The CODEC and the MODEL modules together form compression engine, in which the CODEC provides variable length coding and data packing, and the MODEL implements the LZ processing. The MODEL uses content addressable memory ("CAM") in encoding mode for text storage and character matching, and uses CAM in decoding mode as an on-chip RAM to obtain high speed access.

Abstract translation: 数据压缩/解压缩处理器实现修改的Ziv-Lempel（“LZ”）编码技术。 处理器包括三个模块，一个接口，一个编码器解码器（“CODEC”）和一个MODEL。 CODEC和MODEL模块一起形成压缩引擎，其中CODEC提供可变长度编码和数据打包，MODEL实现LZ处理。 MODEL在编码模式下使用内容可寻址存储器（“CAM”）进行文本存储和字符匹配，并将解码模式下的CAM用作片上RAM以获得高速访问。